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Connect uninitialized signals
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Signed-off-by: Robert Szczepanski <[email protected]>
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@robertszczepanski
robertszczepanski committed Dec 20, 2024
1 parent 22c712a commit 4d8f310
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Showing 9 changed files with 183 additions and 124 deletions.
2 changes: 2 additions & 0 deletions src/ctrl/controller_standby.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,8 @@ module controller_standby
tx_host_nack_o = sel_i2c_i3c ? i3c_tx_host_nack_o : i2c_tx_host_nack_o;
end

assign i2c_rx_queue_flush_o = '0;

controller_standby_i2c #(
.TtiRxDescDataWidth(TtiRxDescDataWidth),
.TtiTxDescDataWidth(TtiTxDescDataWidth),
Expand Down
6 changes: 6 additions & 0 deletions src/ctrl/flow_active.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,12 @@ module flow_active
output i3c_irq_t irq
);

assign dct_write_valid_hw_o ='0;
assign rx_queue_wvalid_o ='0;
assign ibi_queue_wvalid_o ='0;
assign err ='0;
assign irq ='0;

typedef enum logic [3:0] {
Idle = 4'd0,
WaitForCmd = 4'd1,
Expand Down
106 changes: 95 additions & 11 deletions src/hci/hci.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -287,17 +287,6 @@ module hci
hwif_in.DCT = dct_i;
dat_o = hwif_out_o.DAT;
dct_o = hwif_out_o.DCT;

hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR_VALID.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR_VALID.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR.we = '0;

// Addresses

// STBY_CR_DEVICE_CHAR
// STBY_CR_DEVICE_PID_LO
// hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.we = '0;
end : wire_hwif

always_comb begin : wire_hwif_ccc
Expand Down Expand Up @@ -512,4 +501,99 @@ module hci
.reg_rst_data_o(hci_ibi_rst_next)
);

always_comb begin : wire_unconnected_regs
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR_VALID.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.DYNAMIC_ADDR.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR_VALID.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.PENDING_RX_NACK.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.HANDOFF_DELAY_NACK.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.ACR_FSM_OP_SELECT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.PRIME_ACCEPT_GETACCCR.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.HANDOFF_DEEP_SLEEP.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.HANDOFF_DEEP_SLEEP.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.TARGET_XACT_ENABLE.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.TARGET_XACT_ENABLE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETAASA_ENABLE.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETAASA_ENABLE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETDASA_ENABLE.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETDASA_ENABLE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_ENTDAA_ENABLE.we = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.SIMPLE_CRR_SUPPORT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.TARGET_XACT_SUPPORT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETAASA_SUPPORT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETDASA_SUPPORT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_ENTDAA_SUPPORT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_STATUS.AC_CURRENT_OWN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_STATUS.SIMPLE_CRR_STATUS.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_STATUS.HJ_REQ_STATUS.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.ACR_HANDOFF_OK_REMAIN_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.ACR_HANDOFF_OK_PRIMED_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.ACR_HANDOFF_ERR_FAIL_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.ACR_HANDOFF_ERR_M3_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.CRR_RESPONSE_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_DYN_ADDR_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_ACCEPT_NACKED_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_ACCEPT_OK_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_ACCEPT_ERR_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.STBY_CR_OP_RSTACT_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.CCC_PARAM_MODIFIED_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.CCC_UNHANDLED_NACK_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.CCC_FATAL_RSTDAA_ERR_STAT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.ACR_HANDOFF_OK_REMAIN_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.ACR_HANDOFF_OK_PRIMED_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.ACR_HANDOFF_ERR_FAIL_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.ACR_HANDOFF_ERR_M3_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.CRR_RESPONSE_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_DYN_ADDR_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_ACCEPT_NACKED_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_ACCEPT_OK_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_ACCEPT_ERR_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.STBY_CR_OP_RSTACT_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.CCC_PARAM_MODIFIED_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.CCC_UNHANDLED_NACK_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.CCC_FATAL_RSTDAA_ERR_SIGNAL_EN.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CRR_RESPONSE_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_DYN_ADDR_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_NACKED_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_OK_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_ACCEPT_ERR_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.STBY_CR_OP_RSTACT_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_PARAM_MODIFIED_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_UNHANDLED_NACK_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.CCC_FATAL_RSTDAA_ERR_FORCE.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS.F2_CRCAP1_BUS_CONFIG.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS.F2_CRCAP2_DEV_INTERACT.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.next = '0;
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.next = '0;

hwif_in.I3C_EC.CtrlCfg.CONTROLLER_CONFIG.OPERATION_MODE.we = '0;

hwif_in.I3CBase.HC_CONTROL.RESUME.we = '0;
hwif_in.I3CBase.HC_CONTROL.RESUME.next = '0;
hwif_in.I3CBase.HC_CONTROL.BUS_ENABLE.we = '0;
hwif_in.I3CBase.HC_CONTROL.BUS_ENABLE.next = '0;
hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.we = '0;
hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.next = '0;
hwif_in.I3CBase.PRESENT_STATE.AC_CURRENT_OWN.next = '0;
hwif_in.I3CBase.INTR_STATUS.HC_INTERNAL_ERR_STAT.next = '0;
hwif_in.I3CBase.INTR_STATUS.HC_SEQ_CANCEL_STAT.next = '0;
hwif_in.I3CBase.INTR_STATUS.HC_WARN_CMD_SEQ_STALL_STAT.next = '0;
hwif_in.I3CBase.INTR_STATUS.HC_ERR_CMD_SEQ_TIMEOUT_STAT.next = '0;
hwif_in.I3CBase.INTR_STATUS.SCHED_CMD_MISSED_TICK_STAT.next = '0;
hwif_in.I3CBase.DCT_SECTION_OFFSET.TABLE_INDEX.we = '0;
hwif_in.I3CBase.DCT_SECTION_OFFSET.TABLE_INDEX.next = '0;
hwif_in.I3CBase.IBI_DATA_ABORT_CTRL.IBI_DATA_ABORT_MON.we = '0;
hwif_in.I3CBase.IBI_DATA_ABORT_CTRL.IBI_DATA_ABORT_MON.next = '0;

hwif_in.PIOControl.PIO_INTR_STATUS.TX_THLD_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.RX_THLD_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.IBI_STATUS_THLD_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.CMD_QUEUE_READY_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.RESP_READY_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.TRANSFER_ABORT_STAT.next = '0;
hwif_in.PIOControl.PIO_INTR_STATUS.TRANSFER_ERR_STAT.next = '0;
end

endmodule : hci
55 changes: 50 additions & 5 deletions src/hci/tti.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -152,14 +152,59 @@ module tti
ibi_queue_reg_rst_o = hwif_tti_i.RESET_CONTROL.IBI_QUEUE_RST.value;
end : wire_hwif_rst

always_comb begin : wire_int_status
hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.we = '0;
end

always_comb begin
hwif_tti_o.STATUS.LAST_IBI_STATUS.next = ibi_status_i;
hwif_tti_o.STATUS.LAST_IBI_STATUS.we = ibi_status_we_i;
end

always_comb begin : wire_unconnected_regs
hwif_tti_o.RESET_CONTROL.SOFT_RST.we = '0;
hwif_tti_o.RESET_CONTROL.SOFT_RST.next = '0;

hwif_tti_o.STATUS.PROTOCOL_ERROR.next = '0;

hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.we = '0;
hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.RX_DESC_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TX_DESC_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.RX_DESC_TIMEOUT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TX_DESC_TIMEOUT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.RX_DATA_THLD_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TX_DATA_THLD_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.RX_DESC_THLD_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TX_DESC_THLD_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.IBI_THLD_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.IBI_DONE.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.next = '0;
hwif_tti_o.INTERRUPT_STATUS.TRANSFER_ERR_STAT.next = '0;

hwif_tti_o.INTERRUPT_ENABLE.RX_DESC_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TX_DESC_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.RX_DESC_TIMEOUT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TX_DESC_TIMEOUT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.RX_DATA_THLD_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TX_DATA_THLD_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.RX_DESC_THLD_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TX_DESC_THLD_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.IBI_THLD_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.IBI_DONE_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TRANSFER_ABORT_STAT_EN.next = '0;
hwif_tti_o.INTERRUPT_ENABLE.TRANSFER_ERR_STAT_EN.next = '0;

hwif_tti_o.INTERRUPT_FORCE.RX_DESC_STAT_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TX_DESC_STAT_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.RX_DESC_TIMEOUT_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TX_DESC_TIMEOUT_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.RX_DATA_THLD_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TX_DATA_THLD_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.RX_DESC_THLD_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TX_DESC_THLD_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.IBI_THLD_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.IBI_DONE_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TRANSFER_ABORT_STAT_FORCE.next = '0;
hwif_tti_o.INTERRUPT_FORCE.TRANSFER_ERR_STAT_FORCE.next = '0;

hwif_tti_o.QUEUE_THLD_CTRL.IBI_THLD.we = '0;
hwif_tti_o.QUEUE_THLD_CTRL.IBI_THLD.we = '0;
end
endmodule : tti
17 changes: 0 additions & 17 deletions src/i3c.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1039,21 +1039,4 @@ module i3c
.sel_od_pp_i(ctrl_sel_od_pp),
.sel_od_pp_o(sel_od_pp_o)
);

always_comb begin : other_uninit_signals
xcontroller.xcontroller_active.flow_fsm.dct_write_valid_hw_o = 0;
xcontroller.xcontroller_standby.i2c_rx_queue_flush_o = 0;
xrecovery_handler.irq_o = 0;
xrecovery_handler.recv_tti_rx_data_queue_flow = 0;
xcontroller.xcontroller_active.flow_fsm.rx_queue_wvalid_o = 0;
// See the TODO `in src/ctrl/flow_active.sv`
//xcontroller.xcontroller_active.flow_fsm.resp_queue_wvalid_o = 0;
xcontroller.xcontroller_active.flow_fsm.ibi_queue_wvalid_o = 0;

xcontroller.xcontroller_active.flow_fsm.err.err_0 = 0;
xcontroller.xcontroller_active.flow_fsm.irq.irq_0 = 0;
// No proper zero assignment in combo block
//xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.command_code_valid = 0;
end : other_uninit_signals

endmodule
2 changes: 1 addition & 1 deletion src/recovery/recovery_handler.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,6 +173,7 @@ module recovery_handler
output logic payload_available_o,
output logic image_activated_o
);
assign irq_o = '0;

// ....................................................

Expand Down Expand Up @@ -540,7 +541,6 @@ module recovery_handler

logic recv_tti_rx_data_queue_select;
logic recv_tti_rx_data_queue_flush;
logic recv_tti_rx_data_queue_flow;

// RX data queue
always_comb begin : R2MUX
Expand Down
52 changes: 12 additions & 40 deletions verification/cocotb/block/hci_queues_ahb/hci_queues_wrapper.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -161,6 +161,7 @@ module hci_queues_wrapper
input logic tti_rx_wvalid_i,
output logic tti_rx_wready_o,
input logic [7:0] tti_rx_wdata_i,
input logic tti_rx_flush_i,

// TX queue
output logic tti_tx_full_o,
Expand All @@ -174,6 +175,7 @@ module hci_queues_wrapper
output logic tti_tx_rvalid_o,
input logic tti_tx_rready_i,
output logic [7:0] tti_tx_rdata_o,
input logic tti_tx_flush_i,

// In-band Interrupt Queue
output logic tti_ibi_full_o,
Expand All @@ -194,7 +196,11 @@ module hci_queues_wrapper

// Received I2C/I3C address along with RnW# bit
input logic [7:0] bus_addr_i,
input logic bus_addr_valid_i
input logic bus_addr_valid_i,

output logic payload_available_o,
output logic image_activated_o,
output logic irq_o
);

// I3C SW CSR IF
Expand All @@ -211,9 +217,6 @@ module hci_queues_wrapper
logic s_cpuif_wr_ack;
logic s_cpuif_wr_err;

logic tti_rx_flush;
logic tti_tx_flush;

ahb_if #(
.AhbDataWidth(`AHB_DATA_WIDTH),
.AhbAddrWidth(`AHB_ADDR_WIDTH)
Expand Down Expand Up @@ -513,11 +516,11 @@ module hci_queues_wrapper
.hwif_rec_o(hwif_rec_inp),

// Interrupt
.irq_o(irq),
.irq_o(irq_o),

// Recovery status
.payload_available_o(payload_available),
.image_activated_o(image_activated),
.payload_available_o(payload_available_o),
.image_activated_o(image_activated_o),

// ...........................
// TTI CSR interface
Expand Down Expand Up @@ -611,7 +614,7 @@ module hci_queues_wrapper
.ctl_tti_rx_data_queue_wvalid_i(tti_rx_wvalid_i),
.ctl_tti_rx_data_queue_wready_o(tti_rx_wready_o),
.ctl_tti_rx_data_queue_wdata_i(tti_rx_wdata_i),
.ctl_tti_rx_data_queue_flush_i(tti_rx_flush),
.ctl_tti_rx_data_queue_flush_i(tti_rx_flush_i),
.ctl_tti_rx_data_queue_start_thld_o(tti_rx_start_thld_o),
.ctl_tti_rx_data_queue_start_thld_trig_o(tti_rx_start_thld_trig_o),
.ctl_tti_rx_data_queue_ready_thld_o(tti_rx_ready_thld_o),
Expand All @@ -624,7 +627,7 @@ module hci_queues_wrapper
.ctl_tti_tx_data_queue_rvalid_o(tti_tx_rvalid_o),
.ctl_tti_tx_data_queue_rready_i(tti_tx_rready_i),
.ctl_tti_tx_data_queue_rdata_o(tti_tx_rdata_o),
.ctl_tti_tx_data_queue_flush_i(tti_tx_flush),
.ctl_tti_tx_data_queue_flush_i(tti_tx_flush_i),
.ctl_tti_tx_data_queue_start_thld_o(tti_tx_start_thld_o),
.ctl_tti_tx_data_queue_start_thld_trig_o(tti_tx_start_thld_trig_o),
.ctl_tti_tx_data_queue_ready_thld_o(tti_tx_ready_thld_o),
Expand All @@ -641,35 +644,4 @@ module hci_queues_wrapper
.ctl_tti_ibi_queue_ready_thld_o(tti_ibi_ready_thld_o),
.ctl_tti_ibi_queue_ready_thld_trig_o(tti_ibi_ready_thld_trig_o)
);

// TODO: These write-enable signals were not combo-driven or initialized on reset.
// This is a placeholder driver. They require either unimplemented drivers or changes in RDL.
always_comb begin : missing_csr_we_inits
hci.hwif_in.I3CBase.HC_CONTROL.RESUME.we = 0;
hci.hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR.we = 0;
hci.hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR_VALID.we = 0;
hci.hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.we = 0;
hci.hwif_in.I3CBase.DCT_SECTION_OFFSET.TABLE_INDEX.we = 0;
hci.hwif_in.I3CBase.IBI_DATA_ABORT_CTRL.IBI_DATA_ABORT_MON.we = 0;
hci.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.HANDOFF_DEEP_SLEEP.we = 0;
hci.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.TARGET_XACT_ENABLE.we = 0;
hci.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETAASA_ENABLE.we = 0;
hci.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETDASA_ENABLE.we = 0;
hci.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_ENTDAA_ENABLE.we = 0;
hci.hwif_in.I3C_EC.CtrlCfg.CONTROLLER_CONFIG.OPERATION_MODE.we = 0;

hci.hwif_in.I3CBase.HC_CONTROL.BUS_ENABLE.we = 0;

xtti.hwif_tti_o.QUEUE_THLD_CTRL.IBI_THLD.we = 0;
xtti.hwif_tti_o.RESET_CONTROL.IBI_QUEUE_RST.we = 0;
xtti.hwif_tti_o.RESET_CONTROL.SOFT_RST.we = 0;
end : missing_csr_we_inits

always_comb begin : other_uninit_signals
xrecovery_handler.irq_o = 0;
xrecovery_handler.recv_tti_rx_data_queue_flow = 0;
tti_rx_flush = 0;
tti_tx_flush = 0;
end : other_uninit_signals

endmodule
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