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[patch] Fix various typos. (#63)
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dtzSiFive authored and seldridge committed Mar 1, 2023
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62 changes: 32 additions & 30 deletions spec.md
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Expand Up @@ -124,7 +124,7 @@ toolchain.

The FIRRTL specification was originally published as a UC Berkeley Tech Report
([UCB/EECS-2016-9](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9.html))
authored by Adam Izraelevitz ([`@azidar`](https://github.com/azidar)), Partick
authored by Adam Izraelevitz ([`@azidar`](https://github.com/azidar)), Patrick
Li ([`@CuppoJava`](https://github.com/CuppoJava)), and Jonathan Bachrach
([`@jackbackrack`](https://github.com/jackbackrack)). The vision for FIRRTL was
then expanded in an [ICCAD
Expand Down Expand Up @@ -167,7 +167,7 @@ contributors is below:

# File Preamble

A firrtl file begins with a magic string and version identifier indicating the
A FIRRTL file begins with a magic string and version identifier indicating the
version of this standard the file conforms to
(see [@sec:versioning-scheme-of-this-document]). This will not be present on
files generated according to versions of this standard prior to the first
Expand Down Expand Up @@ -279,9 +279,9 @@ FIRRTL's width inferencer, as detailed in [@sec:width-inference].

Integers of width zero are permissible. They are always zero extended.
Thus, when used in an operation that extends to a positive bit width, they
behave like a zero. While zero bit width integer carry no information, we
behave like a zero. While zero bit width integers carry no information, we
allow 0-bit integer constant zeros for convenience:
`UInt<0>(0)` and `SInt<0>(0)`.
`UInt<0>(0)`{.firrtl} and `SInt<0>(0)`{.firrtl}.

``` firrtl
wire zero_u : UInt<0>
Expand Down Expand Up @@ -387,7 +387,7 @@ wire reset : Reset
reset <= a
```

After reset inference, `reset` is inferred to the synchronous
After reset inference, `reset`{.firrtl} is inferred to the synchronous
`UInt<1>`{.firrtl} type:

``` firrtl
Expand Down Expand Up @@ -934,11 +934,12 @@ must be a `Reset`{.firrtl}, `UInt<1>`{.firrtl}, or `AsyncReset`{.firrtl}, and
the type of initialization value must be equivalent to the declared type of the
register (see [@sec:type-equivalence] for details). The behavior of the
register depends on the type of the reset signal. `AsyncReset`.{firrtl} will
immediately change the value of the register. `UInt<1> will not change
the value of the register until the next positive edge of the clock signal (see
[@sec:reset-type]). `Reset`.{firrtl} is an abstract reset whose behavior
depends on reset inference. In the following example, `myreg`{.firrtl} is
assigned the value `myinit`{.firrtl} when the signal `myreset`{.firrtl} is high.
immediately change the value of the register. `UInt<1>`{.firrtl} will not
change the value of the register until the next positive edge of the clock
signal (see [@sec:reset-type]). `Reset`{.firrtl} is an abstract reset whose
behavior depends on reset inference. In the following example, `myreg`{.firrtl}
is assigned the value `myinit`{.firrtl} when the signal `myreset`{.firrtl} is
high.

``` firrtl
wire myclock: Clock
Expand Down Expand Up @@ -1577,16 +1578,16 @@ simulations of the circuit. Backends are free to generate hardware that relays
this information to a hardware test harness, but this is not required by the
FIRRTL specification.

A printf statement requires a clock signal, a print condition signal, a format
string, and a variable list of argument signals. The condition signal must be a
single bit unsigned integer type, and the argument signals must each have a
ground type.
A `printf`{.firrtl} statement requires a clock signal, a print condition signal,
a format string, and a variable list of argument signals. The condition signal
must be a single bit unsigned integer type, and the argument signals must each
have a ground type.

For information about execution ordering of clocked statements with observable
environmental side effects, see [@sec:stops].

The printf statement has an optional name attribute which can be used to attach
metadata to the statement. The name is part of the module level
The `printf`{.firrtl} statement has an optional name attribute which can be used
to attach metadata to the statement. The name is part of the module level
namespace. However it can never be used in a reference since it is not of any
valid type.

Expand All @@ -1598,9 +1599,9 @@ wire b: UInt
printf(clk, cond, "a in hex: %x, b in decimal:%d.\n", a, b) : optional_name
```

On each positive clock edge, when the condition signal is high, the printf
statement prints out the format string where its argument placeholders are
substituted with the value of the corresponding argument.
On each positive clock edge, when the condition signal is high, the
`printf`{.firrtl} statement prints out the format string where its argument
placeholders are substituted with the value of the corresponding argument.

### Format Strings

Expand Down Expand Up @@ -1791,11 +1792,11 @@ The bit representation contains a binary, octal or hex indicator, followed by an
optional sign, followed by the value.

If a bit width is not given, the number of bits in the bit representation is the
minimal bitwidth to represent the value represented by the string. The following
examples create a 8-bit integer representing the number -13. For all bases, a
negative sign acts as if it were a unary negation; in other words, a negative
literal produces the additive inverse of the unsigned interpretation of the
digit pattern.
minimal bit width to represent the value represented by the string. The
following examples create a 8-bit integer representing the number -13. For all
bases, a negative sign acts as if it were a unary negation; in other words, a
negative literal produces the additive inverse of the unsigned interpretation of
the digit pattern.

``` firrtl
SInt("b-1101")
Expand Down Expand Up @@ -2590,7 +2591,7 @@ means that the subclass annotation implies to effect of the parent annotation.

Annotations are serializable to JSON.

Below is an example annotation used to mark some module `foo`:
Below is an example annotation used to mark some module `foo`{.firrtl}:

```json
{
Expand Down Expand Up @@ -2820,11 +2821,12 @@ value (not necessarily literal), at an implementation's discretion, if, in doing
so, all observable behavior is as if the indeterminate value always took the
specific value.

This allows transformations such as the following, where when `a` has an
indeterminate value, the implementation chooses to consistently give it a value
of 'v'. An alternate, legal mapping, lets the implementation give it the value
`42`. In both cases, there is no visibility of `a` when it has an indeterminate
value which is not mapped to the value the implementation chooses.
This allows transformations such as the following, where when `a`{.firrtl} has
an indeterminate value, the implementation chooses to consistently give it a
value of `v`{.firrtl}. An alternate, legal mapping, lets the implementation
give it the value `42`{.firrtl}. In both cases, there is no visibility of
`a`{.firrtl} when it has an indeterminate value which is not mapped to the value
the implementation chooses.

``` firrtl
module IValue :
Expand Down

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