Initial commit for MCI SRAM and MCI AXI SUB module.

config/compilespecs.yml

@@ -4,6 +4,7 @@ files:
   - src/mcu/config/compile.yml
   - src/riscv_core/veer_el2/config/compile.yml
   - src/i3c-core/config/compile.yml
+  - src/mci/config/compile.yml
   - third_party/caliptra-rtl/src/libs/config/compile.yml
   - third_party/caliptra-rtl/src/ahb_lite_bus/config/compile.yml
   - third_party/caliptra-rtl/src/riscv_core/veer_el2/config/compile.yml

src/mci/config/compile.yml

@@ -15,18 +15,24 @@ schema_version: 2.4.0
 requires:
   - caliptra_prim
   - axi_sub
-  - soc_ifc_top
   - mci_pkg
+  # for beh_lib with rvecc_encode/decode
+  - el2_veer_pkg
 targets:
   rtl:
     directories:
       - $COMPILE_ROOT/rtl
     files:
-      - $COMPILE_ROOT/rtl/mci_boot_seqr.sv
       - $COMPILE_ROOT/rtl/mci_top.sv
+      - $COMPILE_ROOT/rtl/mci_axi_sub_decode.sv
+      - $COMPILE_ROOT/rtl/mci_axi_sub_top.sv
+      - $COMPILE_ROOT/rtl/mci_mcu_sram_ctrl.sv
+      - $COMPILE_ROOT/rtl/mci_mcu_sram_if.sv
+      - $COMPILE_ROOT/rtl/cif_if.sv
     tops: [mci_top]
   rtl_lint:
     directories: [$COMPILE_ROOT/config/design_lint]
     waiver_files:
       - $MSFT_REPO_ROOT/src/mci/config/design_lint/mci/sglint_waivers
     tops: [mci_top]
+

src/mci/rtl/cif_if.sv

@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// Description:
+//      Signals for caliptra's internal fabric interface
+//
+
+interface cif_if #(parameter integer ADDR_WIDTH = 32, parameter integer DATA_WIDTH = 32, parameter integer ID_WIDTH = 8, parameter integer USER_WIDTH = 32) (input logic clk, input logic rst_b);
+
+    typedef struct packed {
+        logic                       write;
+        logic   [ADDR_WIDTH-1:0]    addr;
+        logic   [DATA_WIDTH-1:0]    wdata;
+        logic   [DATA_WIDTH/8-1:0]  wstrb;
+        logic   [2:0]               size;
+        logic                       last;
+        logic   [USER_WIDTH-1:0]    user;
+        logic   [ID_WIDTH-1:0]      id;
+    } cif_req_data_t;
+
+    logic                       dv;
+    logic                       hold;
+    logic                       write;
+    logic   [DATA_WIDTH-1:0]    rdata;
+    logic                       error;
+    cif_req_data_t              req_data;
+
+
+    // Modport for read manager
+    modport request (
+
+        output  dv,
+        output  req_data,
+
+        input   hold,
+        input   rdata,
+        input   error
+    );
+
+    // Modport for write manager
+    modport response (
+        input   dv,
+        input   req_data,
+
+        output  hold,
+        output  rdata,
+        output  error
+    );
+
+endinterface

src/mci/rtl/mci_axi_sub_decode.sv

@@ -0,0 +1,108 @@
+
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// Description:
+//      Decodes the SOC request and sends to appropriate target.
+//
+
+module mci_axi_sub_decode 
+    import mci_pkg::*;
+    #(
+    // Configurable memory blocks
+    parameter MCU_SRAM_SIZE_KB = 1024,
+    parameter MBOX0_SIZE_KB    = 4, // KB
+    parameter MBOX1_SIZE_KB    = 4, // KB
+
+
+    ///////////////////////////////////////////////////////////
+    // MCI Memory Map
+    ///////////////////////////////////////////////////////////
+    localparam CSR_SIZE_KB           = 512, // FIXME should I expose? KB
+    localparam CSR_START_ADDR        = 32'h0000_0000,
+    localparam CSR_END_ADDR          = CSR_START_ADDR + (CSR_SIZE_KB * KB) - 1,
+    localparam MBOX0_START_ADDR      = 32'h0008_0000,
+    localparam MBOX0_END_ADDR        = MBOX0_START_ADDR + (MBOX0_SIZE_KB * KB) - 1,
+    localparam MBOX1_START_ADDR      = MBOX0_END_ADDR + 32'h0000_0001, // FIXME: Do we want B2B
+    localparam MBOX1_END_ADDR        = MBOX1_START_ADDR + (MBOX1_SIZE_KB * KB) - 1,
+    localparam MCU_SRAM_START_ADDR   = 32'h0002_0000,
+    localparam MCU_SRAM_END_ADDR     = MCU_SRAM_START_ADDR + (MCU_SRAM_SIZE_KB * KB) - 1
+
+
+    )
+    (
+    //SOC inf
+    cif_if.response  soc_resp_if,
+
+    //MCU SRAM inf
+    cif_if.request  mcu_sram_req_if 
+);
+
+// GRANT signals
+logic soc_mcu_sram_gnt;
+
+// MISC signals
+logic soc_req_miss;
+
+
+///////////////////////////////////////////////////////////
+// Decode which address space is being requested
+///////////////////////////////////////////////////////////
+//SoC requests to MCU_SRAM
+always_comb soc_mcu_sram_gnt = (soc_resp_if.dv & (soc_resp_if.req_data.addr inside {[MCU_SRAM_START_ADDR:MCU_SRAM_END_ADDR]}));
+
+
+///////////////////////////////////////////////////////////
+// Drive DV to appropriate destination
+///////////////////////////////////////////////////////////
+
+// MCU SRAM
+always_comb mcu_sram_req_if.dv = soc_mcu_sram_gnt;
+
+
+///////////////////////////////////////////////////////////
+// Drive data and reqest to approriate destination.
+///////////////////////////////////////////////////////////
+
+// MCU SRAM
+always_comb mcu_sram_req_if.req_data = soc_resp_if.req_data;
+
+
+
+///////////////////////////////////////////////////////////
+// Drive read data back
+///////////////////////////////////////////////////////////
+
+assign soc_resp_if.rdata = soc_mcu_sram_gnt ? mcu_sram_req_if.rdata : '0;
+
+
+///////////////////////////////////////////////////////////
+// Drive approriate hold back
+///////////////////////////////////////////////////////////
+
+always_comb soc_resp_if.hold = (soc_mcu_sram_gnt & (~soc_mcu_sram_gnt | mcu_sram_req_if.hold));
+
+
+///////////////////////////////////////////////////////////
+// Drive approriate error back or request misses all desitnations
+///////////////////////////////////////////////////////////
+
+// Missed all destinations 
+always_comb soc_req_miss = soc_resp_if.dv & ~(soc_mcu_sram_gnt);
+
+// Error for SOC
+always_comb soc_resp_if.error = (soc_mcu_sram_gnt & mcu_sram_req_if.error) |
+                        soc_req_miss;
+
+endmodule

src/mci/rtl/mci_axi_sub_top.sv

@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// Description:
+//      Translates AXI requests to internal fabric. Decoding the requests
+//      and sending to the appropriate target.
+//
+
+
+module mci_axi_sub_top 
+    #(
+    parameter MCU_SRAM_SIZE_KB  = 1024,
+    parameter MBOX0_SIZE_KB    = 4,
+    parameter MBOX1_SIZE_KB    = 4
+    )
+    (
+    input logic clk,
+
+    // MCI Resets
+    input logic rst_b,
+
+    // MCI AXI Interface
+    axi_if.w_sub s_axi_w_if,
+    axi_if.r_sub s_axi_r_if,
+
+    // MCU SRAM Interface
+    cif_if.request  mcu_sram_req_if
+
+    );
+
+localparam AXI_ADDR_WIDTH = s_axi_w_if.AW;
+localparam AXI_DATA_WIDTH = s_axi_w_if.DW;
+localparam AXI_USER_WIDTH = s_axi_w_if.UW;
+localparam AXI_ID_WIDTH   = s_axi_w_if.IW;
+
+// Interface between axi_sub and mci decoder
+cif_if #(
+    .ADDR_WIDTH(AXI_ADDR_WIDTH), 
+    .DATA_WIDTH(AXI_DATA_WIDTH), 
+    .ID_WIDTH(AXI_ID_WIDTH),
+    .USER_WIDTH(AXI_USER_WIDTH)
+    )
+    soc_resp_if(
+        .clk,
+        .rst_b(rst_b)
+    );
+
+//AXI Interface
+//This module contains the logic for interfacing with the SoC over the AXI Interface
+//The SoC sends read and write requests using AXI Protocol
+//This wrapper decodes that protocol, collapses the full-duplex protocol to
+// simplex, and issues requests to the MIC decode block
+axi_sub #(
+    .AW   (AXI_ADDR_WIDTH),
+    .DW   (AXI_DATA_WIDTH),
+    .UW   (AXI_USER_WIDTH),
+    .IW   (AXI_ID_WIDTH  ),
+    .EX_EN(0             ),
+    .C_LAT(0             )
+) i_axi_sub (
+    .clk  (clk     ),
+    .rst_n(rst_b), 
+
+    // AXI INF
+    .s_axi_w_if(s_axi_w_if),
+    .s_axi_r_if(s_axi_r_if),
+
+    //COMPONENT INF
+    .dv    (soc_resp_if.dv  ),
+    .addr  (soc_resp_if.req_data.addr    ), // Byte address
+    .write (soc_resp_if.req_data.write   ),
+    .user  (soc_resp_if.req_data.user    ), 
+    .id    (soc_resp_if.req_data.id      ),
+    .wdata (soc_resp_if.req_data.wdata   ), // Requires: Component dwidth == AXI dwidth
+    .wstrb (soc_resp_if.req_data.wstrb   ), // FIXME unused today Requires: Component dwidth == AXI dwidth
+    .rdata (soc_resp_if.rdata   ), // Requires: Component dwidth == AXI dwidth
+    .last  (soc_resp_if.req_data.last), // FIXME unused in code today Asserted with final 'dv' of a burst
+    .hld   (soc_resp_if.hold    ),
+    .rd_err(soc_resp_if.error   ),
+    .wr_err(soc_resp_if.error   )
+);
+
+assign soc_resp_if.req_data.size = '0; // FIXME unused?
+
+//AXI Interface
+//This module contains the logic for interfacing with the SoC over the AXI Interface
+//The SoC sends read and write requests using AXI Protocol
+//This wrapper decodes that protocol, collapses the full-duplex protocol to
+// simplex, and issues requests to the MIC decode block
+mci_axi_sub_decode #(
+    .MCU_SRAM_SIZE_KB   (MCU_SRAM_SIZE_KB),
+    .MBOX0_SIZE_KB   (MBOX0_SIZE_KB),
+    .MBOX1_SIZE_KB   (MBOX1_SIZE_KB)
+) i_mci_axi_sub_decode (
+    //SOC inf
+    .soc_resp_if        (soc_resp_if.response),
+
+    //MCU SRAM inf
+    .mcu_sram_req_if    (mcu_sram_req_if)
+);
+
+//req from axi is for soc always
+// always_comb soc_req.soc_req = 1'b1; FIXME remove?
+
+
+
+endmodule