AES block with gcm (#664)

* first aes-gcm sync from OT * syn of caliptra prim from OT for aes-gcm integration * sync tlul files from OT for aes-gcm integration * syncing csrng block from OT for update to aes for aes-gcm * script updates for aes-gcm addition * fix for lc ctrl that caused enum definition issues between RTL and TB contexts * updating caliptra top with aes integrated to ahb bus * addition of aes as a keyvault read client and dest_valid bit * Smoke test for aes gcm updates for kv macros to support aes update ahb slv sif to handle unit that drives hold when idle removed hack to tlul adapter * file list updates * fixing PR issues excluding rev info files from license check updated AES smoke test to include more test cases updated AES c library to work for more test cases added AES smoke test to L0 regression * sync latest rev from OT * connecting kv fsm to keymgr interface removed duplicate aes_pkg import. Flagged to lowrisc * stashing spec changes * updating aes with tlul name change * updating hardware spec to include AES information updating compile.yml for name change in tlul modules * fixing bad merge of script * fixing typo in the license header script * updated file list after tlul name change * removing old tlul that stuck around after merge * fixing synth elab issue in aes wrapper * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/aes_gcm_integ' with updated timestamp and hash after successful run
chipsalliance · Dec 21, 2024 · bf69cd3 · bf69cd3
1 parent ada8e02
commit bf69cd3
Show file tree

Hide file tree

Showing 118 changed files with 19,098 additions and 670 deletions.
diff --git a/.github/scripts/license_header_check.sh b/.github/scripts/license_header_check.sh
@@ -78,7 +78,7 @@ exclude_dir='{uvmf*,.git,cmark,caliptra_reg_html,caliptra_top_reg_html,sha256,sh
 exclude_suffix='*.{tcl,txt,js,htm,html,json,vf,yml,woff,rsp,rdl,bashrc,waiver,cfg,hex,rc,exe,pdf,png,hvp,svg,log}'
 exclude_regs='*_reg*.{sv,rdl}'
 exclude_csr='*_csr*.*'
-exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5,riscv_rev_info,caliptra_tlul_rev_info}'
+exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git,.git-comodules,.gitignore,.gitmodules,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c,test_dilithium5,riscv_rev_info,caliptra_tlul_rev_info,aes_rev_info}'
 apache_patn='Licensed under the Apache License\|Apache License, Version 2\.0 (the \"License\")'
 
 # Recursive find through repository with some major exclusions

diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash
@@ -1 +1 @@
-d7522950cee3a6338bddc70db37d2b53d681a16dbab5417c5fede4b899c45ab3998379b3268b2e217f5da423f8c7493c
+1cad8694bd690a699ed8a95772494825b142b6cb12db11fa682a9c71e0865c474b066e6f3c1abe35ce52b03edbac73c1
diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp
@@ -1 +1 @@
-1734561364
+1734735334
diff --git a/docs/CaliptraHardwareSpecification.md b/docs/CaliptraHardwareSpecification.md
@@ -111,6 +111,7 @@ The following table shows the memory map address ranges for each of the IP block
 | SHA512                              | 6         | 32 KiB       | 0x1002_0000   | 0x1002_7FFF |
 | SHA256                              | 10        | 32 KiB       | 0x1002_8000   | 0x1002_FFFF |
 | ML-DSA                              | 14        | 64 KiB       | 0x1003_0000   | 0x1003_FFFF |
+| AES                                 | 15        | 4 KiB        | 0x1001_1000   | 0x1001_1FFF |
 
 #### Peripherals subsystem
 
@@ -1060,7 +1061,7 @@ The ECC architecture inputs and outputs are described in the following table.
 | r\[383:0\]                 | output          | The signature value of the given priveKey/message.                                                                         |
 | s\[383:0\]                 | output          | The signature value of the given priveKey/message.                                                                         |
 | r’\[383:0\]                | Output          | The signature verification result.                                                                                         |
-| DH_sharedkey\[383:0\]      | output          | The generated shared key in the ECDH sharedkey operation.                                                                         |
+| DH_sharedkey\[383:0\]      | output          | The generated shared key in the ECDH sharedkey operation.                                                                  |
 | valid                      | output          | When HIGH, the signal indicates the result is ready.                                                                       |
 
 ### Address map
@@ -1312,6 +1313,52 @@ Please refer to the [Adams-bridge specification](https://github.com/chipsallianc
 ### Address map
 Address map of ML-DSA accelerator is shown here:  [ML-DSA\_reg — clp Reference (chipsalliance.github.io)](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=clp.mldsa_reg)
 
+## AES
+
+The AES unit is a cryptographic accelerator that processes requests from the processor to encrypt or decrypt 16-byte data blocks. It supports AES-128/192/256 in various modes, including Electronic Codebook (ECB), Cipher Block Chaining (CBC), Cipher Feedback (CFB) with a fixed segment size of 128 bits (CFB-128), Output Feedback (OFB), Counter (CTR), and Galois/Counter Mode (GCM).
+
+The AES unit is reused from here, (see [aes](https://github.com/lowRISC/opentitan/tree/master/hw/ip/aes) with a shim to translate from AHB-lite to the tl-ul interface.
+
+Additional registers have been added to support key vault integration. Keys from the key vault can be loaded into the AES unit to be used for encryption or decryption.
+
+### Operation
+
+For more information, see the [AES Programmer's Guide](https://opentitan.org/book/hw/ip/aes/doc/programmers_guide.html).
+
+### Signal descriptions
+
+The AES architecture inputs and outputs are described in the following table.
+
+| Name                               | Input or output | Description  |
+| :--------------------------------- | :-------------- | :----------- |
+| clk                                | input           | All signal timings are related to the rising edge of clk. |
+| reset_n                            | input           | The reset signal is active LOW and resets the core. This is the only active LOW signal.      |
+| DATA_IN                            | input           | Input block to be encrypted or decrypted. Written in four 32-bit registers.       |
+| DATA_OUT                           | output          | Output block result of encryption or decryption. Stored in four 32-bit registers.       |
+| CTRL_SHADOWED.MANUAL_OPERATION     | input           | Configures the AES core to operation in manual mode.       |
+| CTRL_SHADOWED.PRNG_RESEED_RATE     | input           | Configures the rate of reseeding the internal PRNG used for masking.       |
+| CTRL_SHADOWED.SIDELOAD             | input           | When asserted, AES core will use the key from the keyvault interface.       |
+| CTRL_SHADOWED.KEY_LEN              | input           | Configures the AES key length. Supports 128, 192, and 256-bit keys.      |
+| CTRL_SHADOWED.MODE                 | input           | Configures the AES block cipher mode.      |
+| CTRL_SHADOWED.OPERATION            | input           | Configures the AES core to operate in encryption or decryption modes.      |
+| TRIGGER.PRNG_RESEED                | input           | Forces a PRNG reseed.      |
+| TRIGGER.DATA_OUT_CLEAR             | input           | Clears the DATA_OUT registers with pseudo-random data.      |
+| TRIGGER.KEY_IV_DATA_IN_CLEAR       | input           | Clears the Key, IV, and DATA_INT registers with pseudo-random data.      |
+| TRIGGER.START                      | input           | Triggers the encryption/decryption of one data block if in manual operation mode.      |
+| STATUS.ALERT_FATAL_FAULT           | output          | A fatal fault has ocurred and the AES unit needs to be reset.      |
+| STATUS.ALERT_RECOV_CTRL_UPDATE_ERR | output          | An update error has occurred in the shadowed Control Register. <br>
+                                                         AES operation needs to be restarted by re-writing the Control Register. |
+| STATUS.INPUT_READY                 | output          | The AES unit is ready to receive new data input via the DATA_IN registers.      |
+| STATUS.OUTPUT_VALID                | output          | The AES unit has alid output data.      |
+| STATUS.OUTPUT_LOST                 | output          | All previous output data has been fully read by the processor (0) or at least one previous output data block has been lost (1). It has been overwritten by the AES unit before the processor could fully read it. Once set to 1, this flag remains set until AES operation is restarted by re-writing the Control Register. The primary use of this flag is for design verification. This flag is not meaningful if MANUAL_OPERATION=0.      |
+| STATUS.STALL                       | output          | The AES unit is stalled because there is previous output data that must be read by the processor before the AES unit can overwrite this data. This flag is not meaningful if MANUAL_OPERATION=1.      |
+| STATUS.IDLE                        | output          | The AES unit is idle.      |
+
+
+### Address map
+
+The AES address map is shown here: [aes\_clp\_reg — clp Reference (chipsalliance.github.io)](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=clp.aes_clp_reg).
+
 ## PCR vault
 
 * Platform Configuration Register (PCR) vault is a register file that stores measurements to be used by the microcontroller.

diff --git a/src/aes/config/aes.vf b/src/aes/config/aes.vf
@@ -1,11 +1,12 @@
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
-+incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -23,18 +24,21 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v
+${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_trivium_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/keymgr_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
-${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
@@ -69,9 +73,28 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_trivium.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_shadow.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sync_reqack_data.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sync_reqack.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_enc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_dec.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_enc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_dec.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_gf_mult.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_adapter_vh.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_adapter_reg.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_cmd_intg_gen.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_cmd_intg_chk.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_rsp_intg_gen.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_rsp_intg_chk.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_data_integ_dec.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_data_integ_enc.sv
+${CALIPTRA_ROOT}/src/caliptra_tlul/rtl/caliptra_tlul_err.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv
@@ -89,4 +112,25 @@ ${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_control.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_control_fsm.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_control_fsm_n.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_control_fsm_p.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_core.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctr.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctr_fsm.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctr_fsm_n.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctr_fsm_p.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctrl_gcm_reg_shadowed.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ctrl_reg_shadowed.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_ghash.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_clearing.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_reduced_round.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_status.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_top.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_wrap.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_clp_reg_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_clp_reg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_clp_wrapper.sv
diff --git a/src/aes/config/aes_pkg.vf b/src/aes/config/aes_pkg.vf
@@ -1,9 +1,9 @@
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
-+incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
@@ -23,18 +23,21 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v
+${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_trivium_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/keymgr_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
-${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
@@ -69,6 +72,15 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_trivium.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_shadow.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sync_reqack_data.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sync_reqack.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_enc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_39_32_dec.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_enc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_secded_inv_64_57_dec.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_gf_mult.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
diff --git a/src/aes/config/compile.yml b/src/aes/config/compile.yml
@@ -16,6 +16,7 @@ provides: [aes]
 schema_version: 2.4.0
 requires:
   - aes_pkg
+  - caliptra_tlul_pkg
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -38,6 +39,27 @@ targets:
       - $COMPILE_ROOT/rtl/aes_cipher_control.sv
       - $COMPILE_ROOT/rtl/aes_prng_masking.sv
       - $COMPILE_ROOT/rtl/aes_key_expand.sv
+      - $COMPILE_ROOT/rtl/aes_control.sv
+      - $COMPILE_ROOT/rtl/aes_control_fsm.sv
+      - $COMPILE_ROOT/rtl/aes_control_fsm_n.sv
+      - $COMPILE_ROOT/rtl/aes_control_fsm_p.sv
+      - $COMPILE_ROOT/rtl/aes_core.sv
+      - $COMPILE_ROOT/rtl/aes_ctr.sv
+      - $COMPILE_ROOT/rtl/aes_ctr_fsm.sv
+      - $COMPILE_ROOT/rtl/aes_ctr_fsm_n.sv
+      - $COMPILE_ROOT/rtl/aes_ctr_fsm_p.sv
+      - $COMPILE_ROOT/rtl/aes_ctrl_gcm_reg_shadowed.sv
+      - $COMPILE_ROOT/rtl/aes_ctrl_reg_shadowed.sv
+      - $COMPILE_ROOT/rtl/aes_ghash.sv
+      - $COMPILE_ROOT/rtl/aes_prng_clearing.sv
+      - $COMPILE_ROOT/rtl/aes_reduced_round.sv      
+      - $COMPILE_ROOT/rtl/aes_reg_status.sv
+      - $COMPILE_ROOT/rtl/aes_reg_top.sv
+      - $COMPILE_ROOT/rtl/aes_wrap.sv
+      - $COMPILE_ROOT/rtl/aes.sv
+      - $COMPILE_ROOT/rtl/aes_clp_reg_pkg.sv
+      - $COMPILE_ROOT/rtl/aes_clp_reg.sv
+      - $COMPILE_ROOT/rtl/aes_clp_wrapper.sv
     tops: [aes_cipher_core]
   rtl_lint:
     directories: []
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		d7522950cee3a6338bddc70db37d2b53d681a16dbab5417c5fede4b899c45ab3998379b3268b2e217f5da423f8c7493c
		1cad8694bd690a699ed8a95772494825b142b6cb12db11fa682a9c71e0865c474b066e6f3c1abe35ce52b03edbac73c1