Merge branch 'main' into user/dev/michnorris/secret_wires

chipsalliance · Jan 15, 2025 · 7525862 · 7525862
2 parents 2d982c1 + 539740f
commit 7525862
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diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash
@@ -1 +1 @@
-43dfab7a70b0c74173df4e0d3da7140d71725ba41e9fff0d4a55f8ceb5ab777a805162ebdfe08c0595d99644268926de
+5e61d413371d5a568f35e8b41001427a41b5da89e06ed46ccd95fbd75d4abbea6188b71f32957820f65b02561335a431
diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp
@@ -1 +1 @@
-1736301153
+1736885080
diff --git a/src/axi/config/axi_dma.vf b/src/axi/config/axi_dma.vf
@@ -21,6 +21,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv

diff --git a/src/axi/rtl/axi_dma_ctrl.sv b/src/axi/rtl/axi_dma_ctrl.sv
@@ -354,7 +354,7 @@ import soc_ifc_pkg::*;
         endcase
         cmd_inv_byte_count  = |hwif_out.byte_count.count.value[BW-1:0] ||
                               (hwif_out.byte_count.count.value > DMA_MAX_XFER_SIZE) ||
-                              (hwif_out.byte_count.count.value > MBOX_SIZE_BYTES &&
+                              (hwif_out.byte_count.count.value > CPTRA_MBOX_SIZE_BYTES &&
                                ((hwif_out.ctrl.rd_route.value == axi_dma_reg__ctrl__rd_route__rd_route_e__MBOX) ||
                                 (hwif_out.ctrl.wr_route.value == axi_dma_reg__ctrl__wr_route__wr_route_e__MBOX)));
         // power of 2 and word-aligned
@@ -716,7 +716,7 @@ import soc_ifc_pkg::*;
     `CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_BND, wr_req_hshake |-> w_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((w_req_if.addr + w_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n)
     // Proper configuration
     `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_32, DW == 32)
-    `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == MBOX_DATA_W)
+    `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == CPTRA_MBOX_DATA_W)
     // FIFO must have space for all requested data
     `CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC/BC, clk, !rst_n)
     `CALIPTRA_ASSERT(AXI_DMA_OFL_RD_CRED, rd_req_hshake |-> rd_req_byte_count <= FIFO_BC, clk, !rst_n)

diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv
@@ -586,13 +586,13 @@ module caliptra_top_sva
 
   cascade_wdt_t1_service: assert property (
     @(posedge `SVA_RDC_CLK)
-    (`WDT_PATH.wdt_timer1_timeout_serviced && !`WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
+    (`WDT_PATH.wdt_timer1_timeout_serviced_qual && !`WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer1 did not restart after interrupt service");
 
   cascade_wdt_t2_service: assert property (
     @(posedge `SVA_RDC_CLK)
-    (`WDT_PATH.wdt_timer2_timeout_serviced && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+    (`WDT_PATH.wdt_timer2_timeout_serviced_qual && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer2 did not restart after interrupt service");
 
@@ -610,13 +610,13 @@ module caliptra_top_sva
 
   independent_wdt_t1_service: assert property (
     @(posedge `SVA_RDC_CLK)
-    (`WDT_PATH.wdt_timer1_timeout_serviced && `WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
+    (`WDT_PATH.wdt_timer1_timeout_serviced_qual && `WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer1 did not restart after interrupt service");
 
   independent_wdt_t2_service: assert property (
     @(posedge `SVA_RDC_CLK)
-    (`WDT_PATH.wdt_timer2_timeout_serviced && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+    (`WDT_PATH.wdt_timer2_timeout_serviced_qual && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer2 did not restart after interrupt service");
 

diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf
@@ -113,6 +113,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_p
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv

diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf
@@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv

diff --git a/src/integration/config/caliptra_top_tb_pkg.vf b/src/integration/config/caliptra_top_tb_pkg.vf
@@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv

diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf
@@ -125,6 +125,7 @@ ${CALIPTRA_ROOT}/submodules/adams-bridge/src/abr_prim/rtl/abr_prim_sparse_fsm_pk
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/ntt_top/rtl/ntt_defines_pkg.sv
 ${CALIPTRA_ROOT}/submodules/adams-bridge/src/norm_check/rtl/norm_check_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv

diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h
@@ -5279,8 +5279,6 @@
 #define ENTROPY_SRC_REG_MAIN_SM_STATE                                                               (0xe0)
 #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW                                             (0)
 #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK                                            (0x1ff)
-#define CLP_MBOX_SRAM_BASE_ADDR                                                                     (0x30000000)
-#define CLP_MBOX_SRAM_END_ADDR                                                                      (0x3001ffff)
 #define CLP_MBOX_CSR_BASE_ADDR                                                                      (0x30020000)
 #define CLP_MBOX_CSR_MBOX_LOCK                                                                      (0x30020000)
 #define MBOX_CSR_MBOX_LOCK                                                                          (0x0)
@@ -5313,7 +5311,7 @@
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (0x200)
 #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
-#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (0x1fffc00)
+#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (0x3fffc00)
 #define CLP_MBOX_CSR_MBOX_UNLOCK                                                                    (0x30020020)
 #define MBOX_CSR_MBOX_UNLOCK                                                                        (0x20)
 #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -6516,6 +6514,8 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                             (0xa34)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW                   (0)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK                  (0x1)
+#define CLP_MBOX_SRAM_BASE_ADDR                                                                     (0x30040000)
+#define CLP_MBOX_SRAM_END_ADDR                                                                      (0x3007ffff)
 
 
 #endif
diff --git a/src/integration/rtl/caliptra_reg.rdl b/src/integration/rtl/caliptra_reg.rdl
@@ -42,15 +42,6 @@ addrmap clp {
 
     entropy_src entropy_src_reg @ 0x2000_3000;
 
-    mem {name="Mailbox SRAM";
-         desc="Mailbox SRAM for Caliptra direct-mode accesses. Accessible to Caliptra only after acquiring mbox_lock.
-               [br]Caliptra Access: RW
-               [br]SOC Access:      -";
-         memwidth=32;
-         mementries=32768;
-         sw=rw;
-    } external mbox_sram @ 0x3000_0000;
-
     mbox_csr mbox_csr @ 0x3002_0000;
 
     sha512_acc_csr sha512_acc_csr @ 0x3002_1000;
@@ -59,4 +50,13 @@ addrmap clp {
 
     soc_ifc_reg soc_ifc_reg @ 0x3003_0000;
 
+    mem {name="Mailbox SRAM";
+         desc="Mailbox SRAM for Caliptra direct-mode accesses. Accessible to Caliptra only after acquiring mbox_lock.
+               [br]Caliptra Access: RW
+               [br]SOC Access:      -";
+         memwidth=32;
+         mementries=65536;
+         sw=rw;
+    } external mbox_sram @ 0x3004_0000;
+
 };
diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh
@@ -5279,8 +5279,6 @@
 `define ENTROPY_SRC_REG_MAIN_SM_STATE                                                               (32'he0)
 `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW                                             (0)
 `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK                                            (32'h1ff)
-`define CLP_MBOX_SRAM_BASE_ADDR                                                                     (32'h30000000)
-`define CLP_MBOX_SRAM_END_ADDR                                                                      (32'h3001ffff)
 `define CLP_MBOX_CSR_BASE_ADDR                                                                      (32'h30020000)
 `define CLP_MBOX_CSR_MBOX_LOCK                                                                      (32'h30020000)
 `define MBOX_CSR_MBOX_LOCK                                                                          (32'h0)
@@ -5313,7 +5311,7 @@
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (32'h200)
 `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
-`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (32'h1fffc00)
+`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (32'h3fffc00)
 `define CLP_MBOX_CSR_MBOX_UNLOCK                                                                    (32'h30020020)
 `define MBOX_CSR_MBOX_UNLOCK                                                                        (32'h20)
 `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -6516,6 +6514,8 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                             (32'ha34)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW                   (0)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK                  (32'h1)
+`define CLP_MBOX_SRAM_BASE_ADDR                                                                     (32'h30040000)
+`define CLP_MBOX_SRAM_END_ADDR                                                                      (32'h3007ffff)
 
 
 `endif
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
@@ -64,9 +64,9 @@ module caliptra_top
     //SRAM interface for mbox
     output logic mbox_sram_cs,
     output logic mbox_sram_we,
-    output logic [MBOX_ADDR_W-1:0] mbox_sram_addr,
-    output logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata,
-    input  logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata,
+    output logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr,
+    output logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata,
+    input  logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata,
 
     //SRAM interface for imem
     output logic imem_cs,
@@ -257,8 +257,8 @@ module caliptra_top
     pcr_signing_t pcr_signing_data;
 
     //mailbox sram gasket
-    mbox_sram_req_t mbox_sram_req;
-    mbox_sram_resp_t mbox_sram_resp;
+    cptra_mbox_sram_req_t mbox_sram_req;
+    cptra_mbox_sram_resp_t mbox_sram_resp;
 
     logic clear_obf_secrets;
     logic scan_mode_switch;
@@ -286,7 +286,7 @@ module caliptra_top
     logic lsu_addr_ph, lsu_data_ph, lsu_sel;
     logic ic_addr_ph, ic_data_ph, ic_sel;
 
-    logic hmac_busy, ecc_busy, doe_busy, aes_busy;
+    logic hmac_busy, ecc_busy, doe_busy, aes_busy, mldsa_busy;
     logic crypto_error;
 
     always_comb crypto_error = (hmac_busy & ecc_busy) |
@@ -994,6 +994,7 @@ mldsa_top #(
      .kv_read           (kv_read[2]),
      .kv_rd_resp        (kv_rd_resp[2]),
      .pcr_signing_data  (pcr_signing_data),
+     .busy_o            (mldsa_busy),
      .error_intr        (mldsa_error_intr),
      .notif_intr        (mldsa_notif_intr)
 );

diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh
@@ -36,7 +36,7 @@
   // AHB Address Map
   `define CALIPTRA_SLAVE_NAMES         {"AES"        , "MLDSA"      , "ENTROPY_SRC", "CSRNG"      , "IMEM"       , "SHA256"     , "VEER_ICCM_DMA", "VEER_DCCM_DMA", "SOC_IFC"    , "SHA512"     , "DATAVAULT"  , "PCRVAULT"   , "KEYVAULT"   , "HMAC"       , "ECC"        , "DOE_CTRL"   } /* Array of names for peripherals */
   `define CALIPTRA_SLAVE_BASE_ADDR     {32'h1001_1000, 32'h1003_0000, 32'h2000_3000, 32'h2000_2000, 32'h0000_0000, 32'h1002_8000, 32'h4000_0000  , 32'h5000_0000  , 32'h3000_0000, 32'h1002_0000, 32'h1001_C000, 32'h1001_A000, 32'h1001_8000, 32'h1001_0000, 32'h1000_8000, 32'h1000_0000} /* Array with slave base address */
-  `define CALIPTRA_SLAVE_MASK_ADDR     {32'h1001_1FFF, 32'h1003_FFFF, 32'h2000_3FFF, 32'h2000_2FFF, 32'h0000_BFFF, 32'h1002_FFFF, 32'h4001_FFFF  , 32'h5001_FFFF  , 32'h3003_FFFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */
+  `define CALIPTRA_SLAVE_MASK_ADDR     {32'h1001_1FFF, 32'h1003_FFFF, 32'h2000_3FFF, 32'h2000_2FFF, 32'h0001_7FFF, 32'h1002_FFFF, 32'h4001_FFFF  , 32'h5001_FFFF  , 32'h3007_FFFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */
   `define CALIPTRA_SLAVE_ADDR_MASK     (`CALIPTRA_SLAVE_BASE_ADDR ^ `CALIPTRA_SLAVE_MASK_ADDR) /* Array indicating meaningful address bits for each slave */
   `define CALIPTRA_SLAVE_ADDR_WIDTH(n) $clog2((`CALIPTRA_SLAVE_ADDR_MASK >> (`CALIPTRA_AHB_HADDR_SIZE*n)) & {`CALIPTRA_AHB_HADDR_SIZE{1'b1}}) /* Decode address width for each slave from assigned BASE/MASK address */
   `define CALIPTRA_SLAVE_SEL_DOE         0
@@ -90,7 +90,7 @@
   //`define CALIPTRA_KV_NUM_READ 6
   //`define CALIPTRA_KV_NUM_WRITE 4
 
-  `define CALIPTRA_IMEM_BYTE_SIZE   49152
+  `define CALIPTRA_IMEM_BYTE_SIZE   98304
   `define CALIPTRA_IMEM_DATA_WIDTH  64
   `define CALIPTRA_IMEM_DEPTH       `CALIPTRA_IMEM_BYTE_SIZE / (`CALIPTRA_IMEM_DATA_WIDTH/8)
   `define CALIPTRA_IMEM_BYTE_ADDR_W $clog2(`CALIPTRA_IMEM_BYTE_SIZE)

diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml
@@ -22,7 +22,8 @@ contents:
         - ../test_suites/hello_world_iccm/hello_world_iccm.yml
         - ../test_suites/iccm_lock/iccm_lock.yml
         - ../test_suites/c_intr_handler/c_intr_handler.yml
-        - ../test_suites/smoke_test_ecc/smoke_test_ecc.yml
+        - ../test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml
+        - ../test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml
         - ../test_suites/smoke_test_hmac/smoke_test_hmac.yml
         - ../test_suites/smoke_test_mldsa/smoke_test_mldsa.yml
         - ../test_suites/smoke_test_aes/smoke_test_aes.yml
@@ -47,7 +48,8 @@ contents:
         - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
-        - ../test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
+        - ../test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml
+        - ../test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml
         - ../test_suites/smoke_test_hmac_errortrigger/smoke_test_hmac_errortrigger.yml
         - ../test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
         - ../test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml

diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml
@@ -26,7 +26,8 @@ contents:
         - ${CALIPTRA_ROOT}/src/integration/test_suites/hello_world_iccm/hello_world_iccm.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/iccm_lock/iccm_lock.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/c_intr_handler/c_intr_handler.yml
-        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_keygen_sign/smoke_test_ecc_keygen_sign.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_verify_dh/smoke_test_ecc_verify_dh.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hmac/smoke_test_hmac.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hmac_errortrigger/smoke_test_hmac_errortrigger.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.yml
@@ -50,7 +51,8 @@ contents:
         - ${CALIPTRA_ROOT}/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
-        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml

diff --git a/src/integration/stimulus/testsuites/caliptra_top_tb_nightly_random_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_tb_nightly_random_regression.yml
@@ -12,4 +12,6 @@ contents:
         path: "{template_basename}__{seed}.yml"
       templates:
         $CALIPTRA_ROOT/src/integration/test_suites/randomized_pcr_signing/randomized_pcr_signing              : { weight 100 }
-        $CALIPTRA_ROOT/src/integration/test_suites/smoke_test_sha256_wntz_rand/smoke_test_sha256_wntz_rand    : { weight 100 }
+        $CALIPTRA_ROOT/src/integration/test_suites/smoke_test_sha256_wntz_rand/smoke_test_sha256_wntz_rand    : { weight 100 }
+        $CALIPTRA_ROOT/src/integration/test_suites/smoke_test_mldsa_keygen_sign_vfy_rand/smoke_test_mldsa_keygen_sign_vfy_rand    : { weight 100 }
+        $CALIPTRA_ROOT/src/integration/test_suites/smoke_test_mldsa_keygen_standalone_sign_vfy_rand/smoke_test_mldsa_keygen_standalone_sign_vfy_rand    : { weight 100 }
diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv
@@ -94,9 +94,9 @@ module caliptra_top_tb (
     logic mailbox_data_avail;
     logic mbox_sram_cs;
     logic mbox_sram_we;
-    logic [14:0] mbox_sram_addr;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
+    logic [CPTRA_MBOX_ADDR_W-1:0] mbox_sram_addr;
+    logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
+    logic [CPTRA_MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
 
     logic imem_cs;
     logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr;
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		43dfab7a70b0c74173df4e0d3da7140d71725ba41e9fff0d4a55f8ceb5ab777a805162ebdfe08c0595d99644268926de
		5e61d413371d5a568f35e8b41001427a41b5da89e06ed46ccd95fbd75d4abbea6188b71f32957820f65b02561335a431