Merge pull request #51 from chipsalliance/dev-integrate

Rev 0p8 release

README.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2023/03/16*_
+_*Last Update: 2023/03/31*_
 
 
 ## **Tools Used** ##

Release_Notes.md

@@ -0,0 +1,141 @@
+_*SPDX-License-Identifier: Apache-2.0<BR>
+<BR>
+<BR>
+Licensed under the Apache License, Version 2.0 (the "License");<BR>
+you may not use this file except in compliance with the License.<BR>
+You may obtain a copy of the License at<BR>
+<BR>
+http://www.apache.org/licenses/LICENSE-2.0 <BR>
+<BR>
+Unless required by applicable law or agreed to in writing, software<BR>
+distributed under the License is distributed on an "AS IS" BASIS,<BR>
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.<BR>
+See the License for the specific language governing permissions and<BR>
+limitations under the License.*_<BR>
+
+# **Release Notes** #
+_*Last Update: 2023/03/31*_
+
+## Rev 0p8 ##
+
+### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ###
+#### This model is released mainly for interface, floorplan planning purposes for consumers. ####
+#### Rev 0p8 release date: 03-31-2023 ####
+
+- Caliptra IP Specification: see docs/ folder
+- Caliptra Integration Specification: see docs/ folder
+- Caliptra testplan: see docs/ folder
+- CHIPALLIANCE RISC-V Core - https://github.com/chipsalliance/Cores-VeeR-EL2/
+  - ICCM, DCCM enabled w/ 128KB each; Instruction Cache disabled; fast interrupt redirect enabled
+- Cryptos (please see the spec for NIST compliance algorithms followed)
+    - HMAC384 – Caliptra consortium provided (built based on SHA384 block below)
+    - ECC384 – Based on secp384, Caliptra consortium provided
+    - HMAC-DRBG – Caliptra consortium provided (but built using HMAC384 above)
+    - Key Vault & PCR Vault – Caliptra consortium provided
+    - SHA384/SHA512 – https://github.com/secworks/sha512
+    - Deobfuscation block – Built on https://github.com/secworks/aes but NOT ROM/FW accessible
+    - SHA256 – https://github.com/secworks/sha256
+    - Side channel attack analysis and solutions where applicable  (Plz see Caliptra IP specification for details)
+    - AHB-lite internal fabric
+    - Please see spec for decoding details of various blocks
+- Key Vault, PCR Vault w/ HW PCR extension & Data Vault
+- Interrupts from all peripherals (Cryptos, SOC mailbox, IOs, timers etc.)
+- ICCM write locking
+- TAP interface
+- Idle Clock Gating
+- Impactless update reset
+- Mailbox SRAM ECC
+- Security Assert Flushing in debug unlocked & scan modes
+- SOC interface (APB, mailbox, architectural registers, fuse registers, external TRNG REQ, SHA384 acceleration) – Caliptra Consortium provided
+- Lint clean to the rules published in the integration spec
+- HTML (generated from RDLs) for all registers (internal registers, external facing architectural registers, fuse registers)
+- RTL “Frozen” IP interface;  Frozen SOC facing registers.
+    - All changes from hereon forth will require CHIPSALLIACE CALIPTRA WG approval
+- WDT, Integrated TRNG, SPI (unused in BMD/passive mode)
+- Validation Notes:
+    - DUT per crypto block and associated checkers
+    - Nightly regression on crypto blocks on-going
+    - Smoke tests for all of the above passing including bring up/boot of the caliptra IP (KV testing for ECC & SHA)
+    - UVMF for multiple DUT blocks and SOC interface
+    - DV complete for first cut of the boot & reset flows, Fuses, SOC registers, Crypto blocks, Key vault, PCR Vault, PCR extend, PCR signing, Mailbox
+
+## Pending for RTL 1p0: ##
+- Timers, integrated-TRNG integration w/ Caliptra, Error domain logic
+- Lots of bug fixes :-)
+- Data Vault, TRNG REQ protocol, SHA384 acceleration, More mailbox val, PCR val, cross product flows
+
+## Previous Releases ##
+
+### Rev Pre0p8: ###
+#### DISCLAIMER: This is NOT A BUG-FREE MODEL. This is a pre-0p8 development model that will be sync’d every week. ####
+#### This model is released mainly for interface, floorplan planning purposes for consumers. ####
+#### 0p8 release date = 03-31-2023 ####
+- Caliptra Hardware Specification: see docs/ folder
+- Caliptra Integration Specification: see docs/ folder
+- Caliptra testplan: see docs/ folder
+- CHIPALLIANCE RISC-V Core - https://github.com/chipsalliance/Cores-VeeR-EL2/
+  - ICCM, DCCM enabled w/ 128KB each; Instruction Cache disabled; fast interrupt redirect enabled
+-	Cryptos (please see the spec for NIST compliance algorithms followed)
+    -   HMAC384 – Caliptra consortium provided (built based on SHA384 block below)
+    -   ECC384 – Based on secp384, Caliptra consortium provided
+    -   HMAC-DRBG – Caliptra consortium provided (but built using HMAC384 above)
+    -   Key Vault & PCR Vault – Caliptra consortium provided
+    -   SHA384/SHA512 – https://github.com/secworks/sha512
+    -   Deobfuscation block – Built on https://github.com/secworks/aes but NOT ROM/FW accessible
+    -   SHA256 – https://github.com/secworks/sha256
+    -   Side channel attack analysis and solutions where applicable  (Plz see Caliptra IP specification for details)
+-	AHB-lite internal fabric
+    -   Please see spec for decoding details of various blocks
+-	Key Vault, PCR Vault w/ HW PCR extension & Data Vault
+-	Interrupts from all peripherals (Cryptos, SOC mailbox, IOs, timers etc.)
+-	ICCM write locking
+-	TAP interface
+-	Idle Clock Gating
+-	Impactless update reset
+-	Mailbox SRAM ECC
+-	Security Assert Flushing in debug unlocked & scan modes
+-	SOC interface (APB, mailbox, architectural registers, fuse registers, external TRNG REQ, SHA384 acceleration) – Caliptra Consortium provided
+-	Lint clean to the rules published in the integration spec
+-	HTML (generated from RDLs) for all registers (internal registers, external facing architectural registers, fuse registers)
+-	RTL “Frozen” IP interface;  Frozen SOC facing registers.
+    -   All changes from hereon forth will require CHIPSALLIACE CALIPTRA WG approval
+-	Validation Notes:
+    -   DUT per crypto block and associated checkers
+    -   Nightly regression on crypto blocks on-going
+    -   Smoke tests for all of the above passing including bring up/boot of the caliptra IP (KV testing for ECC & SHA)
+    -   UVMF for multiple DUT blocks and SOC interface
+
+### Rev rtl-caliptra_rtl_0.5.1 ###
+-   Add missing printf/ and includes/ directories to src/integration/test_suites which are required to run the tests
+-   Updated Version.txt and tar.gz
+
+### Rev rtl-caliptra_rtl_0.5rtl ###
+-	CHIPALLIANCE RISC-V Core - https://github.com/chipsalliance/Cores-VeeR-EL2
+    - ICCM, DCCM enabled w/ 128KB each; Instruction Cache disabled; fast interrupt redirect enabled
+-	Cryptos (please see the spec for NIST compliance algorithms followed)
+    - HMAC384 – Caliptra consortium provided (built based on SHA384 block below)
+    - ECC384 – Based on secp384, Caliptra consortium provided
+    - HMAC-DRBG – Caliptra consortium provided (but built using HMAC384 above)
+    - Key Vault & PCR Vault – Caliptra consortium provided
+    - SHA384/SHA512 – https://github.com/secworks/sha512
+    - Deobfuscation block – Built on https://github.com/secworks/aes but NOT ROM/FW accessible
+    - SHA256 – https://github.com/secworks/sha256
+    - Side channel attack analysis and solutions where applicable  (Plz see Caliptra IP specification for details)
+-	AHB-lite internal fabric
+    - Please see spec for decoding details of various blocks
+-   Interrupts from all peripherals (Cryptos, SOC mailbox, IOs, timers etc.)
+-	ICCM locking
+-	SOC interface (APB, mailbox, architectural registers, fuse registers, TRNG REQ protocol) – Caliptra Consortium provided
+-	Lint clean up is partially done
+-	HTML (generated from RDLs) for all registers (internal registers, external facing architectural registers, fuse registers)
+-	Stable IP interface (pending TRNG interface wires that is a new feature)
+-	Validation Notes:
+    - DUT per crypto block and associated checkers
+    - Nightly regression on crypto blocks on-going
+    - Smoke tests for all of the above passing including bring up/boot of the caliptra IP (KV testing for ECC & SHA are pending)
+    - UVMF for multiple DUT blocks and SOC interface
+    - NOTE: 0p8 release will have stress validation on SOC interface with random resets, clock gating, impactless update crossed with mailbox protocol etc.
+
+
+
+

src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv

@@ -113,14 +113,14 @@ always_ff @(posedge hclk or negedge hreset_n) begin
     end
     else begin
         //Capture the address during the address phase for each initiator
-        initiator0_pend_haddr <= initiator0_address_ph ? haddr_i_0 : initiator0_pend_haddr;
-        initiator1_pend_haddr <= initiator1_address_ph ? haddr_i_1 : initiator1_pend_haddr;
-        initiator0_pend_htrans <= initiator0_address_ph ? htrans_i_0 : initiator0_pend_htrans;
-        initiator1_pend_htrans <= initiator1_address_ph ? htrans_i_1 : initiator1_pend_htrans;
-        initiator0_pend_hsize <= initiator0_address_ph ? hsize_i_0 : initiator0_pend_hsize;
-        initiator1_pend_hsize <= initiator1_address_ph ? hsize_i_1 : initiator1_pend_hsize;
-        initiator0_pend_hwrite <= initiator0_address_ph ? hwrite_i_0 : initiator0_pend_hwrite;
-        initiator1_pend_hwrite <= initiator1_address_ph ? hwrite_i_1 : initiator1_pend_hwrite;
+        initiator0_pend_haddr <= initiator0_address_ph & ~initiator0_pend_addr_ph ? haddr_i_0 : initiator0_pend_haddr;
+        initiator1_pend_haddr <= initiator1_address_ph & ~initiator1_pend_addr_ph ? haddr_i_1 : initiator1_pend_haddr;
+        initiator0_pend_htrans <= initiator0_address_ph & ~initiator0_pend_addr_ph ? htrans_i_0 : initiator0_pend_htrans;
+        initiator1_pend_htrans <= initiator1_address_ph & ~initiator1_pend_addr_ph ? htrans_i_1 : initiator1_pend_htrans;
+        initiator0_pend_hsize <= initiator0_address_ph & ~initiator0_pend_addr_ph ? hsize_i_0 : initiator0_pend_hsize;
+        initiator1_pend_hsize <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hsize_i_1 : initiator1_pend_hsize;
+        initiator0_pend_hwrite <= initiator0_address_ph & ~initiator0_pend_addr_ph ? hwrite_i_0 : initiator0_pend_hwrite;
+        initiator1_pend_hwrite <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hwrite_i_1 : initiator1_pend_hwrite;
 
         //Capture pending address phase when initiators collide
         initiator0_pend_addr_ph <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator0_gnt;
@@ -145,7 +145,7 @@ always_comb initiator1_hwrite = initiator1_pend_addr_ph ? initiator1_pend_hwrite
 //Select the appropriate initiator
 //Initiator 0 gets priority
 //Stall the grant if initiator 1 is processing a data phase and address phase b2b
-always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & hreadyout_i;// & ~(initiator1_data_ph & initiator1_address_ph);
+always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & hreadyout_i;
 
 //Initiator 1 gets through only if initiator 0 isn't getting granted
 always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & hreadyout_i & ~initiator0_gnt;

src/doe/rtl/doe_defines_pkg.sv

@@ -17,6 +17,7 @@
 `define DOE_DEFINES_PKG
 
 package doe_defines_pkg;
+  import kv_defines_pkg::*;
 
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
@@ -66,7 +67,7 @@ typedef enum logic [1:0] {
 } doe_cmd_e;
 
 typedef struct packed {
-    logic [2:0] dest_sel;
+    logic [KV_ENTRY_ADDR_W-1:0] dest_sel;
     doe_cmd_e cmd;
 } doe_cmd_reg_t;
 

src/doe/rtl/doe_fsm.sv

@@ -77,7 +77,7 @@ typedef enum logic [2:0] {
 
 logic running_uds, running_fe;
 
-logic [2:0] dest_addr, dest_addr_nxt;
+logic [KV_ENTRY_ADDR_W-1:0] dest_addr, dest_addr_nxt;
 logic dest_addr_en;
 logic [DEST_WR_OFFSET_W-1:0] dest_write_offset, dest_write_offset_nxt;
 logic dest_write_offset_en;

src/ecc/rtl/ecc_add_sub_mod_alter.sv

@@ -28,6 +28,7 @@ module ecc_add_sub_mod_alter #(
     // Clock and reset.
     input wire           clk,
     input wire           reset_n,
+    input wire           zeroize,
 
     // DATA PORT
     input  wire                 add_en_i,
@@ -85,6 +86,11 @@ module ecc_add_sub_mod_alter #(
             carry0_reg <= '0;
             ready_o <= 1'b0;
         end
+        else if (zeroize) begin
+            r0_reg <= '0;
+            carry0_reg <= '0;
+            ready_o <= 1'b0;
+        end
         else if (add_en_i) begin 
             r0_reg <= r0;
             carry0_reg <= carry0;

src/ecc/rtl/ecc_arith_unit.sv

@@ -42,6 +42,7 @@ module ecc_arith_unit
     // Clock and reset.
     input wire           clk,
     input wire           reset_n,
+    input wire           zeroize,
 
     // DATA PORT
     input  wire [2 : 0]                     ecc_cmd_i,
@@ -98,6 +99,7 @@ module ecc_arith_unit
         ecc_pm_ctrl_i(
         .clk(clk),
         .reset_n(reset_n),
+        .zeroize(zeroize),
         .ecc_cmd_i(ecc_cmd_i),
         .sca_en_i(sca_en_i),
         .digit_i(digit_in),
@@ -118,6 +120,7 @@ module ecc_arith_unit
         ram_tdp_file_i(
         .clk(clk),
         .reset_n(reset_n),
+        .zeroize(zeroize),
         .ena(1'b1),
         .wea(ecc_instr_s.opcode.add_we),
         .addra(ecc_instr_s.opa_addr),
@@ -149,6 +152,7 @@ module ecc_arith_unit
         // Clock and reset.
         .clk(clk),
         .reset_n(reset_n),
+        .zeroize(zeroize),
 
         // DATA PORT
         .add_en_i(ecc_instr_s.opcode.add_en),
@@ -177,6 +181,13 @@ module ecc_arith_unit
             secret_key      <= '0;
             d_o             <= '0;
         end
+        else if (zeroize) begin
+            reg_dinb_r      <= '0;
+            reg_addr_r      <= '0;
+            reg_web_r       <= 0;
+            secret_key      <= '0;
+            d_o             <= '0;
+        end
         else begin
             if (wr_en_i) begin
                 if (wr_op_sel_i == 1'b0) // Write new register