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@hs-apotell
hs-apotell committed Sep 4, 2022
1 parent e85792f commit 1cbfbf2
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Showing 11 changed files with 1,539 additions and 545 deletions.
752 changes: 674 additions & 78 deletions tests/ArrayInst/ArrayInst.log
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20 changes: 11 additions & 9 deletions tests/LibraryIntercon/LibraryIntercon.log
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Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@ LIB: realLib
${SURELOG_DIR}/tests/LibraryIntercon/driver.svr

LIB: logicLib
${SURELOG_DIR}/tests/LibraryIntercon/top.sv
${SURELOG_DIR}/tests/LibraryIntercon/driver.sv
${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv
${SURELOG_DIR}/tests/LibraryIntercon/top.sv


[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
Expand All @@ -26,30 +26,30 @@ LIB: logicLib

[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".

[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".

[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".

[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".

[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".

[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".

[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg".

[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".

[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top".

[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".

[INF:CP0300] Compilation...

[INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg".
Expand Down Expand Up @@ -164,7 +164,7 @@ bit_select 10
class_defn 8
class_typespec 4
class_var 3
constant 154
constant 160
cont_assign 2
delay_control 3
design 1
Expand All @@ -185,12 +185,14 @@ logic_net 22
logic_typespec 23
logic_var 10
module 28
module_array 3
module_typespec 3
operation 11
package 5
param_assign 18
parameter 18
port 24
range 42
range 45
real_typespec 14
real_var 8
ref_obj 75
Expand Down
65 changes: 51 additions & 14 deletions tests/ModPortArrayBind/ModPortArrayBind.log
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Original file line number Diff line number Diff line change
Expand Up @@ -189,56 +189,56 @@ n<> u<155> t<Top_level_rule> c<1> l<2:1> el<30:1>
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
array_typespec 1
bit_select 4
constant 23
constant 25
cont_assign 2
design 1
gen_scope 4
gen_scope_array 4
hier_path 2
int_typespec 4
interface 3
interface_array 1
interface_typespec 6
interface_array 2
interface_typespec 7
io_decl 3
logic_net 2
logic_typespec 2
logic_var 2
modport 3
module 5
operation 7
operation 8
param_assign 2
parameter 4
port 2
range 2
ref_obj 13
range 3
ref_obj 14
=== UHDM Object Stats End ===
[INF:UH0707] Elaborating UHDM...

=== UHDM Object Stats Begin (Elaborated Model) ===
array_typespec 1
bit_select 8
constant 23
constant 25
cont_assign 4
design 1
gen_scope 6
gen_scope_array 6
hier_path 4
int_typespec 4
interface 3
interface_array 1
interface_typespec 6
interface_array 2
interface_typespec 7
io_decl 3
logic_net 2
logic_typespec 2
logic_var 2
modport 3
module 5
operation 9
operation 10
param_assign 2
parameter 4
port 3
range 2
ref_obj 24
range 3
ref_obj 25
=== UHDM Object Stats End ===
[INF:UH0708] Writing UHDM DB: ../../build/regression/ModPortArrayBind/slpp_all/surelog.uhdm ...

Expand Down Expand Up @@ -360,6 +360,43 @@ design: (work@r5p_bus_dec)
\_interface_typespec: (r5p_bus_if), line:15:3, endln:15:13
|vpiName:man
|vpiIsModPort:1
|vpiInterfaceArray:
\_interface_array: (r5p_bus_if.man), line:15:18, endln:15:19
|vpiParent:
\_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10
|vpiName:m
|vpiFullName:r5p_bus_if.man
|vpiRange:
\_range: , line:15:19, endln:15:27
|vpiLeftRange:
\_operation: , line:15:20, endln:15:24
|vpiParent:
\_range: , line:15:19, endln:15:27
|vpiOpType:11
|vpiOperand:
\_ref_obj: (BN), line:15:20, endln:15:22
|vpiParent:
\_operation: , line:15:20, endln:15:24
|vpiName:BN
|vpiOperand:
\_constant: , line:15:23, endln:15:24
|vpiParent:
\_operation: , line:15:20, endln:15:24
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiConstType:9
|vpiRightRange:
\_constant: , line:15:25, endln:15:26
|vpiParent:
\_range: , line:15:19, endln:15:27
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiElemTypespec:
\_interface_typespec: (r5p_bus_if.man), line:15:3, endln:15:17
|vpiName:r5p_bus_if.man
|uhdmtopModules:
\_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10
|vpiName:work@r5p_bus_dec
Expand Down Expand Up @@ -403,7 +440,7 @@ design: (work@r5p_bus_dec)
\_port: (m), line:15:18, endln:15:19
|vpiFullName:work@r5p_bus_dec.m
|vpiActual:
\_interface_array: (work@r5p_bus_dec.m)
\_interface_array: (work@r5p_bus_dec.m), line:15:18, endln:15:19
|vpiTypedef:
\_interface_typespec: (man), line:15:14, endln:15:17
|vpiParent:
Expand Down Expand Up @@ -461,7 +498,7 @@ design: (work@r5p_bus_dec)
|vpiInterface:
\_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:dut.sv, line:12:0
|vpiInterfaceArray:
\_interface_array: (work@r5p_bus_dec.m)
\_interface_array: (work@r5p_bus_dec.m), line:15:18, endln:15:19
|vpiParent:
\_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10
|vpiName:m
Expand Down
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