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Integrate main-next#84

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tmichalak merged 43 commits intomainchipsalliance/Cores-VeeR-EL2:mainfrom main-nextchipsalliance/Cores-VeeR-EL2:main-nextCopy head branch name to clipboardJun 21, 2023

+1,627-52

Commits

Commits on Feb 20, 2023

• Added a way of injecting user module for clock gate(s)

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Commits on Apr 3, 2023

• Corrected default WIDTH param value of rvdffppe

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Commits on Apr 4, 2023

• Fixed swapped mnemonics in testbench/dasm.svi

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Commits on Apr 6, 2023

• Initial makefile able to run RISC-V DV code in Verilated simulation and in spike ISS

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• End-to-end RISC-V DV flow, currently reports execution mismatch.

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Commits on Apr 11, 2023

• Reworked VeeR execution trace parser

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• Created a temporary assembly code fixup script for VeeR and integrated it with the Makefile flow

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• Updated ld script

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• VeeR execution log parser terminates on first occurrence of ecall instruction

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• Finalized the makefile flow

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Commits on Apr 12, 2023

• Added RISC-V DV as a submodule

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• Changed to use RISC-V DV instruction generator available in the current path

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• Initial RISC-V DV CI

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Commits on Apr 14, 2023

• Merge pull request #77 from antmicro/mkurc/fix-opcode-swap

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  tmichalak

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Commits on Apr 17, 2023

• Bumped RISC-V DV submodule

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• Added dumping CSR writes to the execution log from testbench

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• Support for parsing CSR write effects from VeeR testbench execution logs

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• Added VeeR-ISS (a.k.a. whisper) to the RISC-V DV verification flow

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• Added using VeeR-ISS in the CI

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• Switched to RISC-V DV code generation and ISS invocation done by run.py, added matrix CI

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• Integrated code fixup needed for VeeR with the RISC-V DV flow

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• Fixed handling of execution corner case when a delayed effect insruction attempts writing to x0 (zero)

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• RISC-V DV workflow tweaks

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Commits on Apr 24, 2023

• Merge pull request #79 from antmicro/use-riscv-dv

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Commits on Apr 27, 2023

• Merge pull request #54 from antmicro/user_clock_gate

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  kgugala

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Commits on May 5, 2023

• Merge pull request #76 from antmicro/mkurc/fix-rvdffppe-issue

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  tmichalak

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Commits on May 17, 2023

• Integrated Renode with the RISC-V DV flow

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Commits on May 18, 2023

• Add support for renode

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Commits on May 22, 2023

• Bumped RISC-V DV submodule

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• Separated CI artifact packages for different ISS

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• Added seeding rng in RISC-V DV to the CI

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• Merge pull request #82 from antmicro/mczyz/ci-renode-support

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Commits on May 29, 2023

• Added missing el2_pkg imports

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• lint: waive module-filename rule for libraries

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Commits on Jun 1, 2023

• Merge pull request #85 from antmicro/mkurc/add-missing-imports

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  tmichalak

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Commits on Jun 5, 2023

• Implement minimal PyUVM test environment

  mczyz-antmicro

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• Add mock test for faster CI debugging

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• Run tests in CI

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• Merge pull request #83 from antmicro/mczyz/rebase-pyuvm

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  tmichalak

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Commits on Jun 16, 2023

• Bump versions of actions for node16

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Commits on Jun 19, 2023

• Revert addition of the scan_rst_l input

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  mkurc-ant

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• Merge pull request #90 from antmicro/mczyz/update-riscvdv

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Commits on Jun 20, 2023

• Merge pull request #91 from antmicro/mkurc/sync-veer

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