chore: refine chip docs

ch32-rs · Nov 5, 2023 · 5e79283 · 5e79283
1 parent 40c54b7
commit 5e79283
Show file tree

Hide file tree

Showing 7 changed files with 49 additions and 16 deletions.
diff --git a/docs/CH32L103.md b/docs/CH32L103.md
@@ -1,14 +1,17 @@
 # CH32L103
 
+RISC-V4C, 96MHz, 64KB Flash, 20KB SRAM.
+
+RTC, ADC/TKey, CAN, OPA, CMP, USB-PD/Type-C.
 
 ## Chips
 
 ```
- *  CH32L103C8U6-0x103007x0
- *	CH32L103C8T6-0x103107x0
- * 	CH32L103F8P6-0x103A07x0
- *  CH32L103G8R6-0x103B07x0
- *  CH32L103K8U6-0x103207x0
- *  CH32L103F8U6-0x103D07x0
- *  CH32L103F7P6-0x103707x0
- ```
+* CH32L103C8U6-0x103007x0
+* CH32L103C8T6-0x103107x0
+* CH32L103F8P6-0x103A07x0
+* CH32L103G8R6-0x103B07x0
+* CH32L103K8U6-0x103207x0
+* CH32L103F8U6-0x103D07x0
+* CH32L103F7P6-0x103707x0
+```
diff --git a/docs/CH32V003.md b/docs/CH32V003.md
@@ -1,21 +1,27 @@
 # CH32V003
 
+RISC-V2A, 16KB Flash, 2KB SRAM, 48MHz.
+
 > **Note**
 > CH32V003 is a riscv32ec core, which is not supported by ofiicial Rust yet.
 > ch32-rs team maintains a fork of Rust at <https://github.com/ch32-rs/rust>.
 > You can check [Noxim's Blog](https://noxim.xyz/blog/rust-ch32v003/introduction/) for riscv32ec support.
 
-- [x] Flash support
-- [x] Memory dump support
-- [x] Reset / Resume
-- [x] Reg read/write support
+## Debug support
+
+1-wire debug.
 
 ```text
 SWDIO <-> D1/DIO@MCU, PD1
 GND   <-> GND@MCU
 3V3   <-> 3V3@MCU (No need if you connect your MCU board with USB-C power supply)
 ```
 
+- [x] Flash support
+- [x] Memory dump support
+- [x] Reset / Resume
+- [x] Reg read/write support
+
 ```console
 > wlink -v flash ./firmware.bin
 13:41:49 [INFO] WCH-Link v2.8 (WCH-LinkE-CH32V305)

diff --git a/docs/CH32X035.md b/docs/CH32X035.md
@@ -1,5 +1,11 @@
 # CH32X035
 
+RISC-V4C, 62KB Flash, 20KB SRAM.
+
+OPA/PGA/CMP, USB-PD/Type-C.
+
+## Debug Pins
+
 SWDIO - PC18/DIO @ MCU
 SWCLK - PC19/DCK @ MCU
 

diff --git a/docs/CH56X.md b/docs/CH56X.md
@@ -1,10 +1,17 @@
-# CH569
+# CH569/CH565
 
-## Boards
+RISC-V3A, 448KB Code Flash, 32KB Data Flash, 32/64/96KB SRAM(RAMX).
 
-- CH569W-R0-1v0
+BUS8, USB-SS, ETH, EMMC, SerDes
 
-## Pins
+- CH569: HSPI
+- CH565: DVP
+
+## Debug Pins
 
 - TCK=HTACK=PA10
 - TIO=HTCLK=PA11
+
+## Boards
+
+- CH569W-R0-1v0
diff --git a/docs/CH57x_CH58x_CH59x.md b/docs/CH57x_CH58x_CH59x.md
@@ -1,5 +1,7 @@
 # CH57X & CH58X & CH59X
 
+BLE MCU.
+
 ## Debug Pins
 
 - PB15 TCK

diff --git a/docs/CH641.md b/docs/CH641.md
@@ -1,5 +1,10 @@
 # CH641
 
+RISC-V2A, 48MHz, 16KB Flash, 2KB SRAM.
+
+USB-PD/Type-C, BC1.2, HV DCP.
+ISP/ISN, QII.
+
 > **Note**
 > CH641 is a riscv32ec core, which is not supported by ofiicial Rust yet.
 > ch32-rs team maintains a fork of Rust at <https://github.com/ch32-rs/rust>.

diff --git a/docs/CH643.md b/docs/CH643.md
@@ -1,5 +1,9 @@
 # CH643
 
+RISC-V4C, 62KB Flash, 20KB SRAM.
+
+OPA/PGA/CMP, LEDPWM, USB-PD/Type-C.
+
 ## Chips
 
 ```