Department of Computer Engineering, University of Peradeniya
- 179 followers
- Peradeniya, Sri Lanka
- http://www.ce.pdn.ac.lk/
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- beehive-monitoring-system Public
cepdnaclk/beehive-monitoring-system’s past year of commit activity - projects.ce.pdn.ac.lk Public
This is the student project portfolio website of the Department of Computer Engineering, University of Peradeniya. https://projects.ce.pdn.ac.lk
cepdnaclk/projects.ce.pdn.ac.lk’s past year of commit activity - e20-3yp-Remote-Gait-Analysis Public
cepdnaclk/e20-3yp-Remote-Gait-Analysis’s past year of commit activity - e20-co502-RV32IM_Pipelined_Processor_Group-04 Public
Design and implementation of a 32-bit RISC-V processor supporting the RV32IM instruction set, developed as part of the Advanced Computer Architecture course (CO502). Webpage: https://cepdnaclk.github.io/e20-co502-RV32IM_Pipelined_Processor
cepdnaclk/e20-co502-RV32IM_Pipelined_Processor_Group-04’s past year of commit activity - e20-co502-RV32IM-pipeline-implementation-group-2 Public
This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.
cepdnaclk/e20-co502-RV32IM-pipeline-implementation-group-2’s past year of commit activity - people.ce.pdn.ac.lk Public
Student and staff profile website of the Department of Computer Engineering, University of Peradeniya https://people.ce.pdn.ac.lk/
cepdnaclk/people.ce.pdn.ac.lk’s past year of commit activity - portal.ce.pdn.ac.lk Public
Internal and Public web service provider of the Department of Computer Engineering
cepdnaclk/portal.ce.pdn.ac.lk’s past year of commit activity - e20-co502-RV32IM_Pipelined_Processor_Group-05 Public
The RV32IM pipeline processor project designs a 32-bit RISC-V processor with 5 stages: IF, ID, EX, MEM, WB. It supports RV32I base and M-extension (MUL/DIV), using forwarding, stalling, and branch prediction to manage hazards. Implemented in Verilog, it is simulated, tested with RISC-V tools, and optimized for performance.
cepdnaclk/e20-co502-RV32IM_Pipelined_Processor_Group-05’s past year of commit activity
