MIPS-pipeline-CPU

A simple MIPS pipeline CPU as course experiment for THUEE Fundamental of Digital Logic and Processor 2020

Using Xilinx Basys-3, xc7a35tcpg236-1

• Maximum Frequency: 106.8MHz (With strategies Flow_AlternateRoutability (Vivado Synthesis 2019) and Vivado Implementation Defaults (Vivado Implementation 2019))
• CPI on quicksort: 1.243

See report for more details. (Out of date after 2020.09.20)

Other course experiments for Fundamental of Digital Logic and Processor 2020 could be seen here.