Refactor cpu master check

src/arch/armv8/armv8-a/aarch32/vmm.c

@@ -9,7 +9,7 @@
 
 void vmm_arch_init_tcr()
 {
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         /* Despite LPAE, we only support 32-bit guest physical address spaces. */
         parange = PAR_32BIT;
     }

src/arch/armv8/armv8-a/aarch64/vmm.c

@@ -30,7 +30,7 @@ void vmm_arch_init_tcr()
 
     cpu_sync_barrier(&cpu_glb_sync);
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         parange = min_parange;
         if (parange_table[parange] < 44) {
             for (size_t i = 0; i < vm_pt_dscr->lvls - 1; i++) {

src/arch/armv8/armv8-a/iommu.c

@@ -11,7 +11,7 @@
 
 bool iommu_arch_init()
 {
-    if (cpu()->id == CPU_MASTER && platform.arch.smmu.base) {
+    if (cpu_is_master() && platform.arch.smmu.base) {
         smmu_init();
         return true;
     }

src/arch/armv8/armv8-r/vmm.c

@@ -14,7 +14,7 @@ static uint32_t timer_freq = 0;
 
 void vmm_arch_profile_init()
 {
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         /**
          * Since there is no firmware in cortex-r platforms, we need to initialize the system
          * counter.

src/arch/armv8/gic.c

@@ -78,7 +78,7 @@ void gic_init()
         ISB();
     }
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         gic_map_mmio();
         gicd_init();
         NUM_LRS = gich_num_lrs();

src/arch/riscv/interrupts.c

@@ -17,7 +17,7 @@
 
 void interrupts_arch_init()
 {
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         irqc_init();
     }
 

src/arch/riscv/iommu.c

@@ -422,7 +422,7 @@ void rv_iommu_write_ddt(deviceid_t dev_id, struct vm* vm, paddr_t root_pt)
 bool iommu_arch_init()
 {
     // By checking platform.arch.iommu.base we verify if an IOMMU is present in the platform
-    if (cpu()->id == CPU_MASTER && platform.arch.iommu.base) {
+    if (cpu_is_master() && platform.arch.iommu.base) {
         rv_iommu_init();
         return true;
     }

src/core/console.c

@@ -20,7 +20,7 @@ static spinlock_t console_lock = SPINLOCK_INITVAL;
 
 void console_init()
 {
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         if ((platform.console.base & PAGE_OFFSET_MASK) != 0) {
             WARNING("console base must be page aligned");
         }

src/core/cpu.c

@@ -41,7 +41,7 @@ void cpu_init(cpuid_t cpu_id, paddr_t load_addr)
 
     list_init(&cpu()->interface->event_list);
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         cpu_sync_init(&cpu_glb_sync, platform.cpu_num);
 
         ipi_cpumsg_handler_num = ((size_t)&_ipi_cpumsg_handlers_size) / sizeof(cpu_msg_handler_t);

src/core/inc/cpu.h

@@ -79,6 +79,11 @@ static inline struct cpuif* cpu_if(cpuid_t cpu_id)
     return &cpu_interfaces[cpu_id];
 }
 
+static inline bool cpu_is_master(void)
+{
+    return cpu()->id == CPU_MASTER;
+}
+
 static inline void cpu_sync_init(struct cpu_synctoken* token, size_t n)
 {
     token->lock = SPINLOCK_INITVAL;

src/core/init.c

@@ -26,7 +26,7 @@ void init(cpuid_t cpu_id, paddr_t load_addr)
 
     console_init();
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         console_printk("Bao Hypervisor\n\r");
     }
 

src/core/interrupts.c

@@ -40,7 +40,7 @@ inline void interrupts_init()
 {
     interrupts_arch_init();
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         if (!interrupts_reserve(IPI_CPU_MSG, cpu_msg_handler)) {
             ERROR("Failed to reserve IPI_CPU_MSG interrupt");
         }

src/core/ipc.c

@@ -116,7 +116,7 @@ static void ipc_alloc_shmem()
 
 void ipc_init()
 {
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         shmem_table_size = config.shmemlist_size;
         shmem_table = config.shmemlist;
         ipc_alloc_shmem();

src/core/mem.c

@@ -411,7 +411,7 @@ void mem_init(paddr_t load_addr)
 
     static struct mem_region* root_mem_region = NULL;
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         cache_enumerate();
 
         if (!mem_setup_root_pool(load_addr, &root_mem_region)) {
@@ -435,7 +435,7 @@ void mem_init(paddr_t load_addr)
         mem_color_hypervisor(load_addr, root_mem_region);
     }
 
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         if (!mem_create_ppools(root_mem_region)) {
             ERROR("couldn't create additional page pools");
         }

src/core/mmu/mem.c

@@ -797,7 +797,7 @@ void mem_color_hypervisor(const paddr_t load_addr, struct mem_region* root_regio
      * space, whilst other CPUs only have to copy the image from the CPU_MASTER in order to be able
      * to access it.
      */
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         copy_space(&_image_start, image_size, &p_image);
         va = mem_alloc_vpage(&cpu_new->as, SEC_HYP_IMAGE, (vaddr_t)&_image_start,
             NUM_PAGES(image_size));
@@ -824,7 +824,7 @@ void mem_color_hypervisor(const paddr_t load_addr, struct mem_region* root_regio
      * The root page pool bitmap tracks all the physical allocation, so it needs to be the last
      * thing to be copied, as after that, no physical allocation will be tracked.
      */
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         /* Copy root pool bitmap */
         copy_space((void*)root_pool->bitmap, bitmap_size, &p_bitmap);
         va = mem_alloc_vpage(&cpu_new->as, SEC_HYP_GLOBAL, (vaddr_t)root_pool->bitmap,
@@ -855,7 +855,7 @@ void mem_color_hypervisor(const paddr_t load_addr, struct mem_region* root_regio
      * before they get used again, so CPUs need a way to communicate between themselves without an
      * explicit barrier. To accomplish this a static global variable is used.
      */
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         cpu_sync_init(&cpu_glb_sync, platform.cpu_num);
         shared_pte = 0;
     } else {
@@ -870,7 +870,7 @@ void mem_color_hypervisor(const paddr_t load_addr, struct mem_region* root_regio
      * CPU space regions and Hypervisor image region are contingent, starting from `load_addr`. The
      * bitmap region is on top of the root pool region.
      */
-    if (cpu()->id == CPU_MASTER) {
+    if (cpu_is_master()) {
         p_image = mem_ppages_get(load_addr, NUM_PAGES(image_load_size));
         va = mem_alloc_vpage(&cpu()->as, SEC_HYP_GLOBAL, INVALID_VA, p_image.num_pages);
         mem_map(&cpu()->as, va, &p_image, p_image.num_pages, PTE_HYP_FLAGS);