feat(aclint): add support for aclint sswi

Features:
- IPIs sent via ACLINT instead of SBI ECALLs

src/arch/riscv/aclint.c

@@ -0,0 +1,40 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0 
+ * Copyright (c) Bao Project and Contributors. All rights reserved.
+ */
+
+#include <arch/aclint.h>
+#include <cpu.h>
+#include <bao.h>
+#include <platform.h>
+
+volatile struct aclint_sswi_hw *aclint_sswi;
+
+void aclint_init(){
+    aclint_sswi = (void*) mem_alloc_map_dev(&cpu()->as, SEC_HYP_GLOBAL, INVALID_VA, 
+            platform.arch.aclint_sswi.base, NUM_PAGES(sizeof(struct aclint_sswi_hw)));
+
+}
+
+void aclint_send_ipi(cpuid_t target_hart) {
+    cpuid_t aclint_index = aclint_plat_hart_id_to_sswi_index(target_hart);
+    if(target_hart < platform.cpu_num) {
+        aclint_sswi->setssip[aclint_index] = ACLINT_SSWI_SET_SETSSIP;
+    }
+}
+
+/**
+ * By default aclint hart index is equal to the hart identifier
+ * This may be overwritten on the platform defined code
+ */
+
+__attribute__((weak))
+cpuid_t aclint_plat_sswi_index_to_hart_id(cpuid_t sswi_index){
+    return sswi_index;
+}
+
+__attribute__((weak))
+cpuid_t aclint_plat_hart_id_to_sswi_index(cpuid_t hart_id){
+    return hart_id;
+}
+

src/arch/riscv/arch.mk

@@ -18,6 +18,9 @@ irqc_arch_dir=$(cpu_arch_dir)/irqc/$(IRQC_DIR)
 src_dirs+=$(irqc_arch_dir)
 
 arch-cppflags+=-DIRQC=$(IRQC)
+ifeq ($(ACLINT_PRESENT), 1)
+arch-cppflags+=-DACLINT_PRESENT
+endif
 arch-cflags = -mcmodel=medany -march=rv64g -mstrict-align
 arch-asflags =
 arch-ldflags = 

src/arch/riscv/inc/arch/aclint.h

@@ -0,0 +1,28 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) Bao Project and Contributors. All rights reserved.
+ */
+
+#ifndef ACLINT_H
+#define ACLINT_H
+
+#include <bao.h>
+#include <platform.h>
+
+#define ACLINT_SSWI_MAX_HARTS (4095)
+#define ACLINT_SSWI_SET_SETSSIP (0x1)
+
+struct aclint_sswi_hw {
+    uint32_t setssip [ACLINT_SSWI_MAX_HARTS];
+    uint32_t res;
+} __attribute__((__packed__, aligned(PAGE_SIZE)));
+
+extern volatile struct aclint_sswi_hw *aclint_sswi;
+
+void aclint_init();
+void aclint_send_ipi(cpuid_t hart);
+
+cpuid_t aclint_plat_sswi_index_to_hart_id(cpuid_t sswi_index);
+cpuid_t aclint_plat_hart_id_to_sswi_index(cpuid_t hard_id);
+
+#endif /* ACLINT_H */

src/arch/riscv/inc/arch/platform.h

@@ -26,6 +26,10 @@ struct arch_platform {
         unsigned mode;      // Overall IOMMU mode (Off, Bypass, DDT-lvl)
         irqid_t fq_irq_id;  // Fault Queue IRQ ID (wired)
     } iommu;
+
+    struct {
+        paddr_t base;       // Base address of the ACLINT supervisor software interrupts
+    } aclint_sswi;
 };
 
 #endif /* __ARCH_PLATFORM_H__ */

src/arch/riscv/interrupts.c

@@ -14,11 +14,15 @@
 #include <vm.h>
 #include <arch/csrs.h>
 #include <fences.h>
+#include <arch/aclint.h>
 
 void interrupts_arch_init()
 {
     if (cpu()->id  == CPU_MASTER) {  
         irqc_init();
+        if(DEFINED(ACLINT_PRESENT)){
+            aclint_init();
+        }
     }
 
     /* Wait for master hart to finish irqc initialization */
@@ -34,7 +38,11 @@ void interrupts_arch_init()
 
 void interrupts_arch_ipi_send(cpuid_t target_cpu, irqid_t ipi_id)
 {
-    sbi_send_ipi(1ULL << target_cpu, 0);
+    if (DEFINED(ACLINT_PRESENT)) {
+        aclint_send_ipi(target_cpu);
+    } else {
+        sbi_send_ipi(1ULL << target_cpu, 0);
+    }
 }
 
 void interrupts_arch_cpu_enable(bool en)

src/arch/riscv/objects.mk

@@ -15,3 +15,6 @@ cpu-objs-y+=cpu.o
 cpu-objs-y+=cache.o
 cpu-objs-y+=iommu.o
 cpu-objs-y+=relocate.o
+ifeq ($(ACLINT_PRESENT), 1)
+cpu-objs-y+=aclint.o
+endif

src/platform/qemu-riscv64-virt/virt_desc.c

@@ -26,6 +26,9 @@ struct platform platform = {
         #else 
         #error "unknown IRQC type " IRQC
         #endif
+        #if DEFINED(ACLINT_PRESENT)
+        .aclint_sswi.base = 0x2f00000
+        #endif
     }
 
 };