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Achievement: QuickdrawAchievement: Pull Shark

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arhamhashmi01/README.md

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Hi 👋, I'm Syed Arham Hashmi

A Passionate Computer Engineer

Computer Systems Engineering student passionate about technology and innovation. Proficient in programming languages like Python, Verilog,RISC-V Assembly and C++, I'm eager to contribute meaningfully to the field. Let's connect and explore opportunities together!

arhamhashmi01

micro chip

  • 🔭 I’m currently working on Booting Linux on CVA6 RISC-V Processor Ported on FPGA

  • 🌱 I’m currently learning VLSI | ASIC Design | FPGAs

  • 💬 Ask me about C++ | Verilog | Python | RISC-V Assembly

  • 👯 I’m looking to collaborate on RISC-V

  • 👨‍💻 All of my projects are available at https://github.com/arhamhashmi01

  • 📫 How to reach me [email protected]

【C O N N E C T】

arham hashmi syed arham hashmi s.arham_hashmi

【LANGUAGES & TOOLS】

cplusplus css3 figma git html5 linux matlab mysql oracle python

【S T A T S】




arhamhashmi01

 arhamhashmi01

arhamhashmi01

【G R A P H】



𝚐𝚒𝚝𝚑𝚞𝚋 𝚐𝚛𝚊𝚙𝚑


arhamhashmi01

【R E P O_A C T I V I T Y】





Alt

【Q U O T E S】



City Theme Refresh to see another quote

github contribution grid snake animation

Popular repositories Loading

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  2. RV32I_Single_Cycle RV32I_Single_Cycle Public

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  4. CPU-Scheduling-Algorithm CPU-Scheduling-Algorithm Public

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  5. rv32i-sv rv32i-sv Public

    This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

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  6. verilog_practice verilog_practice Public

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