Exn

.github/workflows/scala.yml

@@ -9,7 +9,7 @@ on:
 jobs:
   build:
 
-    runs-on: ubuntu-18.04
+    runs-on: ubuntu-22.04
 
     steps:
     - name: Set up JDK 1.8
@@ -37,9 +37,9 @@ jobs:
     - name: Install BSV
       id: install-bsv
       run: |
-        wget https://github.com/B-Lang-org/bsc/releases/download/2021.07/bsc-2021.07-ubuntu-18.04.tar.gz
-        tar -xvf bsc-2021.07-ubuntu-18.04.tar.gz
-        mv bsc-2021.07-ubuntu-18.04 bsc
+        wget https://github.com/B-Lang-org/bsc/releases/download/2023.01/bsc-2023.01-ubuntu-22.04.tar.gz
+        tar -xvf bsc-2023.01-ubuntu-22.04.tar.gz
+        mv bsc-2023.01-ubuntu-22.04 bsc
     - name: Build Libs
       env:
         BLUESPECDIR: ${{github.workspace}}/bsc

bin/runbsc

@@ -91,13 +91,13 @@ case "$CMD" in
 	#Run simulation in Bluesim
 	"$BSC" $ARGS -sim $BPATH "$TOP".bsv
 	"$BSC" $ARGS $BPATH -sim -o "$TB".bexe -e "$TB" "$TB".ba
-	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" > "$SIMOUT"	
+	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" | grep -v "\$finish" > "$SIMOUT"
 	;;
     "s")
 	#Run simulation in Verilog
 	"$BSC" $ARGS $BPATH $VPATH $VSIM -vdir $VDIR -simdir $SDIR -u "$TOP".bsv
 	"$BSC" $ARGS $VPATH $VSIM -verilog -vdir $VDIR -simdir $SDIR -o "$TB".bexe -e "$TB" "$VDIR"/"$TB".v
-	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" > "$SIMOUT"
+	timeout "$TOUT"s ./"$TB".bexe | grep -v "WARNING" | grep -v "\$finish" > "$SIMOUT"
 	;;
     "c")
 	rm -f *.bi *.bo *.ba

bscRuntime/libs/BypassRF.v

@@ -1,3 +1,4 @@
+// BypassRF.v
 `ifdef BSV_ASSIGNMENT_DELAY
 `else
  `define BSV_ASSIGNMENT_DELAY

bscRuntime/libs/Ehr.bsv

@@ -1,3 +1,4 @@
+// Ehr.bsv
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
 // 

bscRuntime/libs/Memories.bsv

@@ -1,3 +1,4 @@
+// Memories.bsv
 package Memories;
 
 import GetPut :: *;

bscRuntime/libs/Named.bsv

@@ -1,3 +1,4 @@
+// Named.bsv
 package Named;
 
 import Memories :: *;

bscRuntime/libs/NamedEhr.bsv

@@ -1,3 +1,4 @@
+// NamedEhr.bsv
 package Named;
 
 import RegFile :: *;

bscRuntime/libs/PrioFifo.bsv

@@ -1,3 +1,4 @@
+// PrioFifo.bsv
 package PrioFifo;
 
 import FIFOF :: *;
@@ -11,7 +12,7 @@ module mkNBFIFOF(FIFOF#(dtyp)) provisos (Bits#(dtyp, szdtyp));
    FIFOF#(dtyp) f <- mkFIFOF();
    //allow multiple writes in the same cycle
    RWire#(dtyp) enq_data <- mkRWireSBR();
-   
+
    (*fire_when_enabled*)
    rule doEnq (enq_data.wget() matches tagged Valid.d);
       f.enq(d);
@@ -36,7 +37,7 @@ module mkNBFIFOF(FIFOF#(dtyp)) provisos (Bits#(dtyp, szdtyp));
    method Bool notEmpty();
       return f.notEmpty();
    endmethod
-   
+
    method Action clear();
       f.clear();
    endmethod

bscRuntime/libs/Speculation.bsv

@@ -1,3 +1,4 @@
+// Speculation.bsv
 package Speculation;
 
 import Vector :: *;

bscRuntime/libs/nametb.bsv

@@ -1,3 +1,4 @@
+// nametb.bsv
 import Named::*;
 import FIFO::*;
 

bscRuntime/libs/project/build.properties

@@ -0,0 +1 @@
+sbt.version=1.6.2

bscRuntime/libs/tb.bsv

@@ -1,3 +1,4 @@
+// tb.bsv
 import Memories :: *;
 import Connectable :: *;
 

bscRuntime/memories/Ehr.bsv

@@ -1,3 +1,4 @@
+// Ehr.bsv
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
 // 

bscRuntime/memories/Interrupt.bsv

@@ -0,0 +1,35 @@
+package Interrupt;
+
+import FIFOF :: *;
+import Ehr :: *;
+
+interface TimingInterruptController#(numeric type addr);
+    method ActionValue#(Bool) req(Int#(addr) a);
+    method Action ack(Int#(addr) a);
+endinterface
+
+module mkTimingInterruptController(TimingInterruptController#(addr) _unused_);
+
+    Reg#(Bool) status <- mkReg(False);
+    Reg#(UInt#(10)) timer <- mkReg(0);
+    Wire#(Int#(addr)) getAck <- mkWire();
+
+    // rule to update timer and set status to True every 1000 cycle
+    rule updateTimer;
+        timer <= timer + 1;
+        if (timer == 999) begin
+            timer <= 0;
+            status <= True;
+        end
+    endrule
+
+    method ActionValue#(Bool) req(Int#(addr) p);
+        return status;
+    endmethod
+
+    method Action ack(Int#(addr) a);
+        status <= False;
+    endmethod
+endmodule
+
+endpackage