Merge branch 'antonblanchard:master' into fix-vunit

Makefile

@@ -291,7 +291,7 @@ check_vunit:
 
 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 
-check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
+check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython tests_console tests_unit
 
 $(tests): core_tb
 	@./scripts/run_test.sh $@

common.vhdl

@@ -263,6 +263,10 @@ package common is
 	valid: std_ulogic;
 	stop_mark : std_ulogic;
 	nia: std_ulogic_vector(63 downto 0);
+        prefixed: std_ulogic;
+        prefix: std_ulogic_vector(25 downto 0);
+        illegal_suffix: std_ulogic;
+        misaligned_prefix: std_ulogic;
 	insn: std_ulogic_vector(31 downto 0);
 	decode: decode_rom_t;
         br_pred: std_ulogic; -- Branch was predicted to be taken
@@ -274,7 +278,9 @@ package common is
         reg_c : gspr_index_t;
     end record;
     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
-        (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
+        (valid => '0', stop_mark => '0', nia => (others => '0'),
+         prefixed => '0', prefix => (others => '0'), insn => (others => '0'),
+         illegal_suffix => '0', misaligned_prefix => '0',
          decode => decode_rom_init, br_pred => '0', big_endian => '0',
          spr_info => spr_id_init, ram_spr => ram_spr_info_init,
          reg_a => (others => '0'), reg_b => (others => '0'), reg_c => (others => '0'));
@@ -359,9 +365,12 @@ package common is
         ramspr_write_odd   : std_ulogic;
         dbg_spr_access : std_ulogic;
         dec_ctr : std_ulogic;
+        prefixed : std_ulogic;
+        illegal_suffix : std_ulogic;
+        misaligned_prefix : std_ulogic;
     end record;
     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
-	(valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
+	(valid => '0', unit => ALU, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
          write_reg_enable => '0',
          lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0',
 	 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
@@ -378,6 +387,7 @@ package common is
          ramspr_wraddr => (others => '0'), ramspr_write_even => '0', ramspr_write_odd => '0',
          dbg_spr_access => '0',
          dec_ctr => '0',
+         prefixed => '0', illegal_suffix => '0', misaligned_prefix => '0',
          others => (others => '0'));
 
     type MultiplyInputType is record
@@ -500,6 +510,7 @@ package common is
         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
         is_32bit : std_ulogic;
+        prefixed : std_ulogic;
         repeat : std_ulogic;
         second : std_ulogic;
         e2stall : std_ulogic;
@@ -514,7 +525,7 @@ package common is
          addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
          write_reg => (others => '0'),
          length => (others => '0'),
-         mode_32bit => '0', is_32bit => '0',
+         mode_32bit => '0', is_32bit => '0', prefixed => '0',
          repeat => '0', second => '0', e2stall => '0',
          msr => (others => '0'));
 

core.vhdl

@@ -521,6 +521,7 @@ begin
 	    core_stopped => dbg_core_is_stopped,
 	    nia => fetch1_to_icache.nia,
             msr => ctrl_debug.msr,
+            wb_snoop_in => wb_snoop_in,
             dbg_gpr_req => dbg_gpr_req,
             dbg_gpr_ack => dbg_gpr_ack,
             dbg_gpr_addr => dbg_gpr_addr,

core_debug.vhdl

@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 library work;
 use work.utils.all;
 use work.common.all;
+use work.wishbone_types.all;
 
 entity core_debug is
     generic (
@@ -32,6 +33,7 @@ entity core_debug is
         core_stopped    : in std_ulogic;
         nia             : in std_ulogic_vector(63 downto 0);
         msr             : in std_ulogic_vector(63 downto 0);
+        wb_snoop_in     : in wishbone_master_out := wishbone_master_out_init;
 
         -- GPR/FPR register read port
         dbg_gpr_req     : out std_ulogic;
@@ -104,6 +106,7 @@ architecture behave of core_debug is
     constant DBG_CORE_LOG_ADDR       : std_ulogic_vector(3 downto 0) := "0110";
     constant DBG_CORE_LOG_DATA       : std_ulogic_vector(3 downto 0) := "0111";
     constant DBG_CORE_LOG_TRIGGER    : std_ulogic_vector(3 downto 0) := "1000";
+    constant DBG_CORE_LOG_MTRIGGER   : std_ulogic_vector(3 downto 0) := "1001";
 
     constant LOG_INDEX_BITS : natural := log2(LOG_LENGTH);
 
@@ -125,7 +128,11 @@ architecture behave of core_debug is
     signal log_dmi_addr        : std_ulogic_vector(31 downto 0) := (others => '0');
     signal log_dmi_data        : std_ulogic_vector(63 downto 0) := (others => '0');
     signal log_dmi_trigger     : std_ulogic_vector(63 downto 0) := (others => '0');
+    signal log_mem_trigger     : std_ulogic_vector(63 downto 0) := (others => '0');
     signal do_log_trigger      : std_ulogic := '0';
+    signal do_log_mtrigger     : std_ulogic := '0';
+    signal trigger_was_log     : std_ulogic := '0';
+    signal trigger_was_mem     : std_ulogic := '0';
     signal do_dmi_log_rd       : std_ulogic;
     signal dmi_read_log_data   : std_ulogic;
     signal dmi_read_log_data_1 : std_ulogic;
@@ -156,6 +163,7 @@ begin
         log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
         log_dmi_data    when DBG_CORE_LOG_DATA,
         log_dmi_trigger when DBG_CORE_LOG_TRIGGER,
+        log_mem_trigger when DBG_CORE_LOG_MTRIGGER,
         (others => '0') when others;
 
     -- DMI writes
@@ -174,16 +182,27 @@ begin
                 log_trigger_delay <= 0;
                 gspr_index <= (others => '0');
                 log_dmi_addr <= (others => '0');
+                trigger_was_log <= '0';
+                trigger_was_mem <= '0';
             else
-                if do_log_trigger = '1' or log_trigger_delay /= 0 then
+                if do_log_trigger = '1' or do_log_mtrigger = '1' or log_trigger_delay /= 0 then
                     if log_trigger_delay = 255 or
                         (LOG_LENGTH < 1024 and log_trigger_delay = LOG_LENGTH / 4) then
-                        log_dmi_trigger(1) <= '1';
+                        log_dmi_trigger(1) <= trigger_was_log;
+                        log_mem_trigger(1) <= trigger_was_mem;
                         log_trigger_delay <= 0;
+                        trigger_was_log <= '0';
+                        trigger_was_mem <= '0';
                     else
                         log_trigger_delay <= log_trigger_delay + 1;
                     end if;
                 end if;
+                if do_log_trigger = '1' then
+                    trigger_was_log <= '1';
+                end if;
+                if do_log_mtrigger = '1' then
+                    trigger_was_mem <= '1';
+                end if;
                 -- Edge detect on dmi_req for 1-shot pulses
                 dmi_req_1 <= dmi_req;
                 if dmi_req = '1' and dmi_req_1 = '0' then
@@ -217,6 +236,8 @@ begin
                             do_dmi_log_rd <= '1';
                         elsif dmi_addr = DBG_CORE_LOG_TRIGGER then
                             log_dmi_trigger <= dmi_din;
+                        elsif dmi_addr = DBG_CORE_LOG_MTRIGGER then
+                            log_mem_trigger <= dmi_din;
                         end if;
                     else
                         report("DMI read from " & to_string(dmi_addr));
@@ -347,7 +368,7 @@ begin
 
     begin
         -- Use MSB of read addresses to stop the logging
-        log_wr_enable <= not (log_read_addr(31) or log_dmi_addr(31) or log_dmi_trigger(1));
+        log_wr_enable <= not (log_read_addr(31) or log_dmi_addr(31) or log_dmi_trigger(1) or log_mem_trigger(1));
 
         log_ram: process(clk)
         begin
@@ -398,6 +419,13 @@ begin
                     log_dmi_trigger(0) = '1' then
                     do_log_trigger <= '1';
                 end if;
+                do_log_mtrigger <= '0';
+                if (wb_snoop_in.cyc and wb_snoop_in.stb and wb_snoop_in.we) = '1' and
+                    wb_snoop_in.adr = log_mem_trigger(wishbone_addr_bits + wishbone_log2_width - 1
+                                                      downto wishbone_log2_width) and
+                    log_mem_trigger(0) = '1' then
+                    do_log_mtrigger <= '1';
+                end if;
             end if;
         end process;
         log_write_addr(LOG_INDEX_BITS - 1 downto 0) <= std_ulogic_vector(log_wr_ptr);

dcache.vhdl

@@ -341,7 +341,7 @@ architecture rtl of dcache is
         end_row_ix       : row_in_line_t;
         rows_valid       : row_per_line_valid_t;
         acks_pending     : unsigned(2 downto 0);
-        inc_acks         : std_ulogic;
+        stalled          : std_ulogic;
         dec_acks         : std_ulogic;
         choose_victim    : std_ulogic;
         victim_way       : way_t;
@@ -633,14 +633,20 @@ begin
                 addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
                 valid := d_in.valid;
             end if;
-            -- If we have any op and the previous op isn't finished,
+            -- If the previous op isn't finished,
             -- then keep the same output for next cycle.
-            if r0_stall = '0' and valid = '1' then
-                assert not is_X(addrbits);
-                index := to_integer(unsigned(addrbits));
-                tlb_valid_way <= dtlb_valids(index);
-                tlb_tag_way <= dtlb_tags(index);
-                tlb_pte_way <= dtlb_ptes(index);
+            if r0_stall = '0' then
+                assert not (valid = '1' and is_X(addrbits));
+                if is_X(addrbits) then
+                    tlb_valid_way <= (others => 'X');
+                    tlb_tag_way <= (others => 'X');
+                    tlb_pte_way <= (others => 'X');
+                else
+                    index := to_integer(unsigned(addrbits));
+                    tlb_valid_way <= dtlb_valids(index);
+                    tlb_tag_way <= dtlb_tags(index);
+                    tlb_pte_way <= dtlb_ptes(index);
+                end if;
             end if;
             if rst = '1' then
                 tlb_read_valid <= '0';
@@ -1414,15 +1420,16 @@ begin
                 r1.wb.stb <= '0';
                 r1.ls_valid <= '0';
                 r1.mmu_done <= '0';
+                r1.acks_pending <= to_unsigned(0, 3);
+                r1.stalled <= '0';
+                r1.dec_acks <= '0';
 
 		-- Not useful normally but helps avoiding tons of sim warnings
 		r1.wb.adr <= (others => '0');
             else
 		-- One cycle pulses reset
 		r1.slow_valid <= '0';
                 r1.write_bram <= '0';
-                r1.inc_acks <= '0';
-                r1.dec_acks <= '0';
 
                 r1.ls_valid <= '0';
                 -- complete tlbies and TLB loads in the third cycle
@@ -1509,6 +1516,19 @@ begin
                     r1.choose_victim <= '1';
                 end if;
 
+                -- Update count of pending acks
+                acks := r1.acks_pending;
+                if r1.wb.cyc = '0' then
+                    acks := to_unsigned(0, 3);
+                elsif r1.wb.stb = '1' and r1.stalled = '0' and r1.dec_acks = '0' then
+                    acks := acks + 1;
+                elsif (r1.wb.stb = '0' or r1.stalled = '1') and r1.dec_acks = '1' then
+                    acks := acks - 1;
+                end if;
+                r1.acks_pending <= acks;
+                r1.stalled <= wishbone_in.stall and r1.wb.cyc;
+                r1.dec_acks <= wishbone_in.ack and r1.wb.cyc;
+
 		-- Main state machine
 		case r1.state is
                 when IDLE =>
@@ -1563,7 +1583,6 @@ begin
                     when OP_STORE_HIT | OP_STORE_MISS =>
                         if req.dcbz = '0' then
                             r1.state <= STORE_WAIT_ACK;
-                            r1.acks_pending <= to_unsigned(1, 3);
                             r1.full <= '0';
                             r1.slow_valid <= '1';
                             if req.mmu_req = '0' then
@@ -1657,15 +1676,6 @@ begin
 
                 when STORE_WAIT_ACK =>
 		    stbs_done := r1.wb.stb = '0';
-                    acks := r1.acks_pending;
-                    if r1.inc_acks /= r1.dec_acks then
-                        if r1.inc_acks = '1' then
-                            acks := acks + 1;
-                        else
-                            acks := acks - 1;
-                        end if;
-                    end if;
-                    r1.acks_pending <= acks;
 		    -- Clear stb when slave accepted request
                     if wishbone_in.stall = '0' then
                         -- See if there is another store waiting to be done
@@ -1691,7 +1701,6 @@ begin
                             -- Store requests never come from the MMU
                             r1.ls_valid <= '1';
                             stbs_done := false;
-                            r1.inc_acks <= '1';
                         else
                             r1.wb.stb <= '0';
                             stbs_done := true;
@@ -1706,7 +1715,6 @@ begin
                             r1.wb.cyc <= '0';
                             r1.wb.stb <= '0';
                         end if;
-                        r1.dec_acks <= '1';
 		    end if;
 
                 when NC_LOAD_WAIT_ACK =>