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util_axis_fifo_asym: Updated parameters according to HDL changes
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Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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IstvanZsSzekely committed Mar 8, 2024
1 parent 5f94a4c commit 9e51c0d
Showing 1 changed file with 5 additions and 4 deletions.
9 changes: 5 additions & 4 deletions util_axis_fifo_asym/system_bd.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -53,14 +53,15 @@ create_bd_port -dir I output_clk
ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \
ASYNC_CLK 1 \
S_DATA_WIDTH $INPUT_WIDTH \
S_ADDRESS_WIDTH 5 \
ADDRESS_WIDTH 5 \
M_DATA_WIDTH $OUTPUT_WIDTH \
M_AXIS_REGISTERED 1 \
ALMOST_EMPTY_THRESHOLD 4 \
ALMOST_FULL_THRESHOLD 4 \
ALMOST_EMPTY_THRESHOLD 16 \
ALMOST_FULL_THRESHOLD 16 \
TLAST_EN 1 \
TKEEP_EN 1 \
S_FIFO_LIMITED 0 \
FIFO_LIMITED 1 \
ADDRESS_WIDTH_PERSPECTIVE 0 \
]

ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk
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