Fix tests to consider new constraints of HDL Core Version 2.1

Signed-off-by: Travis F. Collins <[email protected]>
analogdevicesinc · Sep 25, 2024 · 9d730c7 · 9d730c7
1 parent 72a525a
commit 9d730c7
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Showing 2 changed files with 24 additions and 17 deletions.
diff --git a/tests/test_adrv9009.py b/tests/test_adrv9009.py
@@ -37,10 +37,15 @@ def test_adrv9009_rx_ad9528_solver_compact(solver):
     sys.clock.d = [*range(1, 257)]  # Limit output dividers
 
     cfg = sys.solve()
-    print(cfg)
+    # print(cfg)
+    from pprint import pprint
+
+    pprint(cfg)
 
     ref = {
-        "gekko": {"clock": {"r1": 2, "n2": 12, "m1": 5, "out_dividers": [6, 9, 192]}},
+        "gekko": {
+            "clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 32, 256]}
+        },
         "CPLEX": {"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 256]}},
     }
 
@@ -89,7 +94,9 @@ def test_adrv9009_tx_ad9528_solver_compact(solver):
     print(cfg)
 
     ref = {
-        "gekko": {"clock": {"r1": 2, "n2": 12, "m1": 5, "out_dividers": [6, 9, 192]}},
+        "gekko": {
+            "clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 32, 256]}
+        },
         "CPLEX": {"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 256]}},
     }
 

diff --git a/tests/test_utils.py b/tests/test_utils.py
@@ -44,56 +44,56 @@ def test_generate_max_rates_fpga_utility():
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 2500000000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 2062500000.0,
+            "bit_clock": 10312500000.0,
             "L": 8,
             "M": 2,
             "quick_configuration_mode": "19.0",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 625000000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 515625000.0,
+            "bit_clock": 10312500000.0,
             "L": 3,
             "M": 3,
             "quick_configuration_mode": "9.01",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 1250000000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 1031250000.0,
+            "bit_clock": 10312500000.0,
             "L": 8,
             "M": 4,
             "quick_configuration_mode": "18.0",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 625000000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 515625000.0,
+            "bit_clock": 10312500000.0,
             "L": 6,
             "M": 6,
             "quick_configuration_mode": "15.01",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 625000000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 515625000.0,
+            "bit_clock": 10312500000.0,
             "L": 8,
             "M": 8,
             "quick_configuration_mode": "16.0",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 312500000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 257812500.0,
+            "bit_clock": 10312500000.0,
             "L": 6,
             "M": 12,
             "quick_configuration_mode": "15.1",
             "jesd_class": "jesd204b",
         },
         {
-            "sample_clock": 312500000.0,
-            "bit_clock": 12500000000.0,
+            "sample_clock": 257812500.0,
+            "bit_clock": 10312500000.0,
             "L": 8,
             "M": 16,
             "quick_configuration_mode": "17.0",