Fix ADRV9009 tests

Signed-off-by: Travis F. Collins <[email protected]>
analogdevicesinc · Sep 27, 2024 · 77961f7 · 77961f7
1 parent 5f3e24a
commit 77961f7
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/tests/test_adrv9009.py b/tests/test_adrv9009.py
@@ -49,15 +49,16 @@ def test_adrv9009_rxtx_ad9528_solver_compact(solver, converter):
     pprint(cfg)
 
     ref = {
-        "gekko": {"clock": {"r1": 1, "n2": 8, "m1": 4, "out_dividers": [1, 8, 256]}},
+        "gekko": {"clock": {"r1": 1, "n2": 8, "m1": 4, "out_dividers": [1, 4, 8, 256]}},
         "CPLEX": {"clock": {"r1": 1, "n2": 8, "m1": 4, "out_dividers": [1, 8, 256]}},
     }
 
     assert cfg["clock"]["r1"] == ref[solver]["clock"]["r1"]
     assert cfg["clock"]["n2"] == ref[solver]["clock"]["n2"]
     assert cfg["clock"]["m1"] == ref[solver]["clock"]["m1"]
     assert (
-        cfg["clock"]["output_clocks"][f"{converter.upper()}_fpga_ref_clk"]["rate"] == 122880000.0
+        cfg["clock"]["output_clocks"][f"{converter.upper()}_fpga_ref_clk"]["rate"]
+        == 122880000.0
     )  # 98304000
     for div in cfg["clock"]["out_dividers"]:
         assert div in ref[solver]["clock"]["out_dividers"]