Fix lint issues from PR

Signed-off-by: Travis F. Collins <[email protected]>

adijif/clocks/ad9528.py

@@ -223,19 +223,24 @@ def b(self, value: Union[int, List[int]]) -> None:
         self._b = value
 
     @property
-    def vco(self):
+    def vco(self) -> float:
+        """VCO Frequency in Hz.
+
+        Returns:
+            float: computed VCO frequency
+        """
         r1 = self._get_val(self.config["r1"])
         m1 = self._get_val(self.config["m1"])
         n2 = self._get_val(self.config["n2"])
 
         return self.vcxo / r1 * m1 * n2
 
     @property
-    def sysref(self):
-        """SYSREF Frequency
+    def sysref(self) -> int:
+        """SYSREF Frequency in Hz.
 
         Returns:
-            float: computed sysref frequency
+            int: computed sysref frequency
         """
         r1 = self._get_val(self.config["r1"])
         k = self._get_val(self.config["k"])
@@ -248,7 +253,12 @@ def sysref(self):
         return sysref_src / (2 * k)
 
     @sysref.setter
-    def sysref(self, value: Union[int, float]):
+    def sysref(self, value: Union[int, float]) -> None:
+        """Set sysref frequency.
+
+        Args:
+            value (int, float): Frequency
+        """
         self._sysref = int(value)
 
     def get_config(self, solution: CpoSolveResult = None) -> Dict:
@@ -416,7 +426,7 @@ def set_requested_clocks(
             self._add_equation([sysref_src / (2 * self.config["k"]) == self._sysref])
 
         # Add requested clocks to output constraints
-        for out_freq, name in zip(out_freqs, clk_names):
+        for out_freq, name in zip(out_freqs, clk_names):  # noqa: B905
             # od = self.model.Var(integer=True, lb=1, ub=256, value=1)
             od = self._convert_input(self._d, f"d_{name}_{out_freq}")
             # od = self.model.sos1([n*n for n in range(1,9)])

adijif/converters/ad9081.py

@@ -349,13 +349,10 @@ def __init__(
         self.set_quick_configuration_mode("3.01", "jesd204b")
 
     def _converter_clock_config(self) -> None:
-        """RX specific configuration of internall PLL config.
+        """RX specific configuration of internal PLL config.
 
         This method will update the config struct to include
         the RX clocking constraints
-
-        Raises:
-            Exception: If solver is not valid
         """
         adc_clk = self.decimation * self.sample_clock
         self.config["l"] = self._convert_input([1, 2, 3, 4], "l")
@@ -470,9 +467,6 @@ def _converter_clock_config(self) -> None:
 
         This method will update the config struct to include
         the TX clocking constraints
-
-        Raises:
-            Exception: If solver is not valid
         """
         dac_clk = self.interpolation * self.sample_clock
         self.config["dac_clk"] = self._convert_input(dac_clk)
@@ -574,9 +568,6 @@ def get_required_clocks(self) -> List:
 
         Returns:
             List: List of solver variables, equations, and constants
-
-        Raises:
-            Exception: If direct clocking is used. Not yet implemented
         """
         # SYSREF
         self.config = {}

adijif/converters/adrv9009.py

@@ -4,9 +4,7 @@
 
 import numpy as np
 
-from adijif.common import core
 from adijif.converters.adrv9009_bf import adrv9009_bf
-from adijif.gekko_trans import gekko_translation
 
 from ..solvers import CpoModel  # type: ignore # noqa: I202,BLK100
 from ..solvers import GEKKO, CpoSolveResult

tests/test_system.py

@@ -1,3 +1,5 @@
+# flake8: noqa
+
 import pytest
 
 import adijif