plat-ls: Add support for armv8 platform flavour

Added support for armv8 platform flavour. - PLATFORM = ls-ls1012ardb Signed-off-by: Pankaj Gupta <[email protected]> Reviewed-by: Sumit Garg <[email protected]> Acked-by: Jens Wiklander <[email protected]> Acked-by: Jerome Forissier <[email protected]>
analogdevicesinc · Nov 15, 2017 · 2863328 · 2863328
1 parent cc45d72
commit 2863328
Show file tree

Hide file tree

Showing 6 changed files with 19 additions and 0 deletions.
diff --git a/.shippable.yml b/.shippable.yml
@@ -136,6 +136,7 @@ build:
     - _make PLATFORM=ls-ls1021aqds
     - _make PLATFORM=ls-ls1043ardb CFG_ARM64_core=y
     - _make PLATFORM=ls-ls1046ardb CFG_ARM64_core=y
+    - _make PLATFORM=ls-ls1012ardb CFG_ARM64_core=y
     - _make PLATFORM=zynq7k-zc702
     - _make PLATFORM=zynqmp-zcu102
     - _make PLATFORM=zynqmp-zcu102 CFG_ARM64_core=y

diff --git a/.travis.yml b/.travis.yml
@@ -226,6 +226,9 @@ script:
   # NXP LS1046A-RDB (ARMv8-A)
   - $make PLATFORM=ls-ls1046ardb CFG_ARM64_core=y
 
+  # NXP LS1012A-RDB (ARMv8-A)
+  - $make PLATFORM=ls-ls1012ardb CFG_ARM64_core=y
+
   # Xilinx Zynq7000 ZC702
   - $make PLATFORM=zynq7k-zc702
 

diff --git a/MAINTAINERS.md b/MAINTAINERS.md
@@ -13,6 +13,7 @@ for these platforms.
 | NXP LS1021A				|`Sumit Garg <[email protected]>`|
 | NXP LS1043A-RDB			|`Sumit Garg <[email protected]>`|
 | NXP LS1046A-RDB			|`Sumit Garg <[email protected]>`|
+| NXP LS1012A-RDB			|`Pankaj Gupta <[email protected]>`|
 | FSL i.MX6 Quad SABRE Lite Board	|`Yan Yan <[email protected]>`,`Feng Yu <[email protected]>`|
 | FSL i.MX6 Quad SABRE SD Board		|`Yan Yan <[email protected]>`,`Feng Yu <[email protected]>`|
 | FSL i.MX6 UltraLite EVK Board		|`Peng Fan <[email protected]>`|

diff --git a/README.md b/README.md
@@ -50,6 +50,7 @@ platforms have different sub-maintainers, please refer to the file
 | [FSL ls1021a](http://www.freescale.com/tools/embedded-software-and-tools/hardware-development-tools/tower-development-boards/mcu-and-processor-modules/powerquicc-and-qoriq-modules/qoriq-ls1021a-tower-system-module:TWR-LS1021A?lang_cd=en)|`PLATFORM=ls-ls1021atwr`| Yes |
 | [NXP ls1043ardb](http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/developer-resources/qoriq-ls1043a-reference-design-board:LS1043A-RDB)|`PLATFORM=ls-ls1043ardb`| Yes |
 | [NXP ls1046ardb](http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/developer-resources/qoriq-ls1046a-reference-design-board:LS1046A-RDB)|`PLATFORM=ls-ls1046ardb`| Yes |
+| [NXP ls1012ardb](http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/developer-resources/qoriq-ls1012a-reference-design-board:LS1012A-RDB)|`PLATFORM=ls-ls1012ardb`| Yes |
 | [FSL i.MX6 Quad SABRE Lite Board](https://boundarydevices.com/product/sabre-lite-imx6-sbc/) |`PLATFORM=imx-mx6qsabrelite`| Yes |
 | [FSL i.MX6 Quad SABRE SD Board](http://www.nxp.com/products/software-and-tools/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-6quad-applications-processors:RD-IMX6Q-SABRE) |`PLATFORM=imx-mx6qsabresd`| Yes |
 | [FSL i.MX6 UltraLite EVK Board](http://www.freescale.com/products/arm-processors/i.mx-applications-processors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/i.mx6ultralite-evaluation-kit:MCIMX6UL-EVK) |`PLATFORM=imx-mx6ulevk`| Yes |

diff --git a/core/arch/arm/plat-ls/conf.mk b/core/arch/arm/plat-ls/conf.mk
@@ -20,6 +20,10 @@ CFG_BOOT_SYNC_CPU ?= y
 CFG_BOOT_SECONDARY_REQUEST ?= y
 endif
 
+ifeq ($(PLATFORM_FLAVOR),ls1012ardb)
+include core/arch/arm/cpu/cortex-armv8-0.mk
+endif
+
 ifeq ($(PLATFORM_FLAVOR),ls1043ardb)
 include core/arch/arm/cpu/cortex-armv8-0.mk
 endif

diff --git a/core/arch/arm/plat-ls/platform_config.h b/core/arch/arm/plat-ls/platform_config.h
@@ -93,6 +93,15 @@
 #define CFG_TEE_CORE_NB_CORE		4
 #endif
 
+#if defined(PLATFORM_FLAVOR_ls1012ardb)
+#define DRAM0_SIZE			0x40000000
+#define CFG_DDR_TEETZ_RESERVED_START	0xBC000000
+#define CFG_DDR_TEETZ_RESERVED_SIZE	0x04000000
+#define CFG_TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
+#define CFG_PUB_RAM_SIZE		(2 * 1024 * 1024)
+#define CFG_TEE_CORE_NB_CORE		1
+#endif
+
 #define DDR_PHYS_START			DRAM0_BASE
 #define DDR_SIZE			DRAM0_SIZE