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fix(SDHC): Fix SDHC Driver Clock Divider for MAX78002 #800

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merged 12 commits into from
Dec 22, 2023

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Jake-Carter
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Description

Closes #797 and implements #791 for the MAX780002

Ports the MAX78002 SDHC_FAT example using the new CLI for #770

Also reduces the default SDHC_CLK_FREQ to 30Mhz, since MAX78002 initializes with the 60Mhz ISO by default.

Checklist Before Requesting Review

  • PR Title follows correct guidelines.
  • Description of changes and all other relevant information.
  • (Optional) Link any related GitHub issues using a keyword
  • (Optional) Provide info on any relevant functional testing/validation. For API changes or significant features, this is not optional.

@github-actions github-actions bot added the MAX78002 Related to the MAX78002 (AI87) label Nov 17, 2023
@Jake-Carter Jake-Carter changed the title fix(SDHC): Fix SDHC Driver Clock Divider for MAX78002 fix(SDHC): Fix SDHC Driver Clock Divider for MAX78002 Nov 17, 2023
Comment on lines 299 to 305
// if (SystemCoreClock > 96000000) {
// printf("SD clock ratio (at card) 4:1\n");
// MXC_SDHC_Set_Clock_Config(1);
// } else {
// printf("SD clock ratio (at card) 2:1\n");
// MXC_SDHC_Set_Clock_Config(0);
// }
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Are we leaving these in just in case?

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Thanks, good catch. I was, but they can be removed now

@Jake-Carter Jake-Carter merged commit 934bdb3 into analogdevicesinc:main Dec 22, 2023
7 of 8 checks passed
@Jake-Carter Jake-Carter deleted the fix/sdhc-clk-ai87 branch December 22, 2023 21:08
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Successfully merging this pull request may close these issues.

MAX78002 SDHC Raw example sets SD clock incorrectly.
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