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fix(Examples,PeriphDrivers): Fix SPI FIFO register access causing swapped message ordering and other minor fixes #755

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merged 7 commits into from
Oct 6, 2023
Merged

fix(Examples,PeriphDrivers): Fix SPI FIFO register access causing swapped message ordering and other minor fixes #755

merged 7 commits into from
Oct 6, 2023

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sihyung-maxim
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Description

  • Fix SPI FIFO register access which can cause the swapped message ordering for some parts (e.g. Transmitting or receiving the expected 00 01 02 03 message results in 01 00 03 02).
  • Add missing SPI_ControllerTarget ssIdx selection on AI87
  • Remove leftover comments in AI87 spi.h
  • Fix TFT_Demo makefile changes.

Checklist Before Requesting Review

  • PR Title follows correct guidelines.
  • Description of changes and all other relevant information.
  • (Optional) Link any related GitHub issues using a keyword
  • (Optional) Provide info on any relevant functional testing/validation. For API changes or significant features, this is not optional.

@github-actions github-actions bot added the MAX78002 Related to the MAX78002 (AI87) label Oct 6, 2023
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/clang-format-run

@sihyung-maxim sihyung-maxim merged commit 80c484d into main Oct 6, 2023
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@sihyung-maxim sihyung-maxim deleted the fix/spi_fifo branch October 6, 2023 18:44
EricB-ADI pushed a commit that referenced this pull request Nov 21, 2023
@sihyung-maxim @EricB-ADI
fix(Examples,PeriphDrivers): Fix SPI FIFO register access causing swa…
2760d1a 
…pped message ordering and other minor fixes (#755)

Co-authored-by: sihyung-maxim <[email protected]>
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@lorne-maxim lorne-maxim lorne-maxim approved these changes

@Jake-Carter Jake-Carter Jake-Carter approved these changes

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MAX78002 Related to the MAX78002 (AI87)
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@sihyung-maxim @Jake-Carter @lorne-maxim