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fix(PeriphDrivers): Resolve incorrect DMA request in DMA-based SPI transactions for all parts #1059

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merged 6 commits into from
Jul 2, 2024
Merged

fix(PeriphDrivers): Resolve incorrect DMA request in DMA-based SPI transactions for all parts #1059

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3c2e57e
fix(PeriphDrivers): always pass valid reqselTx/Rx to MXC_SPI_RevA1_Ma…
JeonChangmin Jun 25, 2024
5fbbe46
fix(PeriphDrivers): always pass valid reqselTx/Rx to MXC_SPI_RevA1_Sl…
JeonChangmin Jun 25, 2024
0680d6b
refactor(PeriphDrivers): merge reqselTx/Rx setting in MXC_SPI_MasterT…
JeonChangmin Jun 25, 2024
4674b6f
refactor(PeriphDrivers): merge reqselTx/Rx setting in MXC_SPI_RevA1_S…
JeonChangmin Jun 25, 2024
049b11e
fix(PeriphDrivers): fix wrong reqselTx/Rx assigment in DMA-based SPI …
JeonChangmin Jun 26, 2024
6bcc398
fix(PeriphDrivers): fix wrong spi_num - reqselTx/Rx match in DMA-base…
JeonChangmin Jul 2, 2024
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81 changes: 25 additions & 56 deletions Libraries/PeriphDrivers/Source/SPI/spi_ai87.c
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Original file line number Diff line number Diff line change
Expand Up @@ -403,34 +403,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;

default:
return E_BAD_PARAM;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

default:
return E_BAD_PARAM;
}
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
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AI87 implementation has SPI0/SPI1 swapped as well. Should be reqselTx = MXC_DMA_REQUEST_SPI0TX; here.

Not your fault, this was there before your fix.

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I believe the original implementation was correct. SPI0 and SPI1 are swapped in several places as an unfortunate result of incorrect documentation, and it's been stuck like that ever since to prevent breaking projects... It's why we have messes like this for the ME17, AI85, and AI87.
image

I say we fix this even if it might break existing projects. Usually, instance 0 is mapped to the lowest peripheral address, and then everything goes in ascending order:

  1. SPI0 (APB) - 0x40046000
  2. SPI1 (APB) - 0x40047000
  3. SPI[n] (APB) - 0x4004m000
  4. SPI[n+1] (AHB) - 0x400BE000
  5. SPI[n+2] (AHB) - 0x400BE400

However, the ME17, AI85, and AI87 doesn't follow this:

  1. SPI0 (AHB) - 0x400BE000
  2. SPI1 (APB) - 0x40046000

This has caused confusion, but it'll be a major breaking change to swap the SPI instance names. Instead, we can fix the MXC_SPI_GET_* definitions in the {device}.h file where SPI0 would be associated with index 0, and SPI1 with index 1. This would still be a breaking change, but it would at least help keep all the indexing aligned with the correct SPI names.

What do you think? @Jake-Carter & @lorne-maxim

reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand All @@ -457,36 +442,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
break;
}
}
case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

default:
return E_BAD_PARAM;
break;
}
default:
return E_BAD_PARAM;
break;
}

return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand Down
79 changes: 24 additions & 55 deletions Libraries/PeriphDrivers/Source/SPI/spi_es17.c
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Original file line number Diff line number Diff line change
Expand Up @@ -252,35 +252,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;

default:
return E_BAD_PARAM;
}
}

//tx
if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand All @@ -307,34 +291,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}
default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand Down
78 changes: 24 additions & 54 deletions Libraries/PeriphDrivers/Source/SPI/spi_me11.c
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Original file line number Diff line number Diff line change
Expand Up @@ -250,34 +250,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPIMSSTX;
break;

default:
return E_BAD_PARAM;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPIMSSRX;
break;

default:
return E_BAD_PARAM;
}
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPIMSSTX;
reqselRx = MXC_DMA_REQUEST_SPIMSSRX;
break;

default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand All @@ -304,34 +289,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPIMSSTX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPIMSSTX;
reqselRx = MXC_DMA_REQUEST_SPIMSSRX;
break;

default:
return E_BAD_PARAM;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPIMSSRX;
break;

default:
return E_BAD_PARAM;
}
default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand Down
81 changes: 25 additions & 56 deletions Libraries/PeriphDrivers/Source/SPI/spi_me12.c
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -359,34 +359,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;

default:
return E_BAD_PARAM;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

default:
return E_BAD_PARAM;
}

return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand All @@ -413,36 +398,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
spi_num = MXC_SPI_GET_IDX(req->spi);
MXC_ASSERT(spi_num >= 0);

if (req->txData != NULL) {
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
break;

case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
break;

default:
return E_BAD_PARAM;
break;
}
}

if (req->rxData != NULL) {
switch (spi_num) {
case 0:
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;
switch (spi_num) {
case 0:
reqselTx = MXC_DMA_REQUEST_SPI1TX;
reqselRx = MXC_DMA_REQUEST_SPI1RX;
break;

case 1:
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;
case 1:
reqselTx = MXC_DMA_REQUEST_SPI0TX;
reqselRx = MXC_DMA_REQUEST_SPI0RX;
break;

default:
return E_BAD_PARAM;
break;
}
default:
return E_BAD_PARAM;
break;
}

return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx,
Expand Down
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