feat(CMSIS): Enable SPIXF cache controller (SFCC) in SystemInit for M…

…AX32572 (#930)
analogdevicesinc · Feb 23, 2024 · c7dc246 · c7dc246
1 parent dd18bc8
commit c7dc246
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c
@@ -122,6 +122,9 @@ __weak void SystemInit(void)
     /* Make sure interrupts are enabled. */
     __enable_irq();
 
+    /* Enable SPIXF cache */
+    MXC_SFCC_Enable();
+
     /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
     /* Grant full access, per "Table B3-24 CPACR bit assignments". */
     /* DDI0403D "ARMv7-M Architecture Reference Manual" */