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@Jake-Carter
Jake-Carter committed Nov 28, 2023
1 parent 514bddc commit c1eb833
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Showing 4 changed files with 58 additions and 58 deletions.
2 changes: 1 addition & 1 deletion Examples/MAX78000/FTHR_SRAM/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ int main(void)
printf("QSPI SRAM Test:\n");
printf("\tTest Address: 0x%x\n", TEST_ADDR);
printf("\tTest size: %i bytes\n", TEST_SIZE);
printf("\tTest speed: %i Hz\n", SPI_SPEED);
printf("\tTest speed: %i Hz\n", FASTSPI_SPEED);

// Time the measurement overhead of our measurement functions
MXC_TMR_SW_Start(MXC_TMR0);
Expand Down
26 changes: 13 additions & 13 deletions Libraries/Boards/MAX78000/FTHR_RevA/Include/fastspi_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,28 +42,28 @@
#include "gpio.h"

// (*) Required definitions:
#define SPI MXC_SPI0
#define SPI_SPEED 25000000
#define FASTSPI_INSTANCE MXC_SPI0
#define FASTSPI_SPEED 25000000

// Optional definitions to make GPIO creation easier:
#define SPI_PINS_PORT MXC_GPIO0
#define SPI_VSSEL MXC_GPIO_VSSEL_VDDIOH
#define SPI_PINS_MASK \
#define FASTSPI_PINS_PORT MXC_GPIO0
#define FASTSPI_VSSEL MXC_GPIO_VSSEL_VDDIOH
#define FASTSPI_PINS_MASK \
(MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9)
#define SPI_SS_PORT MXC_GPIO0
#define SPI_SS_PIN MXC_GPIO_PIN_10 // (SS2)
#define FASTSPI_SS_PORT MXC_GPIO0
#define FASTSPI_SS_PIN MXC_GPIO_PIN_10 // (SS2)

// (*) Required GPIO definitions:
static const mxc_gpio_cfg_t fastspi_ss_pin = { .port = SPI_SS_PORT,
.mask = SPI_SS_PIN,
static const mxc_gpio_cfg_t fastspi_ss_pin = { .port = FASTSPI_SS_PORT,
.mask = FASTSPI_SS_PIN,
.func = MXC_GPIO_FUNC_ALT2, // ALT2 for SS2
.pad = MXC_GPIO_PAD_WEAK_PULL_UP,
.vssel = SPI_VSSEL };
.vssel = FASTSPI_VSSEL };

static const mxc_gpio_cfg_t fastspi_spi_pins = { .port = SPI_PINS_PORT,
.mask = SPI_PINS_MASK,
static const mxc_gpio_cfg_t fastspi_spi_pins = { .port = FASTSPI_PINS_PORT,
.mask = FASTSPI_PINS_MASK,
.func = MXC_GPIO_FUNC_ALT1,
.pad = MXC_GPIO_PAD_NONE,
.vssel = SPI_VSSEL };
.vssel = FASTSPI_VSSEL };

#endif // LIBRARIES_BOARDS_MAX78000_FTHR_REVA_INCLUDE_FASTSPI_CONFIG_H_
72 changes: 36 additions & 36 deletions Libraries/MiscDrivers/SRAM/fastspi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,8 @@ void DMA_RX_IRQHandler()
void processSPI()
{
// Unload any SPI data that has come in
while (g_rx_buffer && (SPI->dma & MXC_F_SPI_DMA_RX_LVL) && g_rx_len > 0) {
*g_rx_buffer++ = SPI->fifo8[0];
while (g_rx_buffer && (FASTSPI_INSTANCE->dma & MXC_F_SPI_DMA_RX_LVL) && g_rx_len > 0) {
*g_rx_buffer++ = FASTSPI_INSTANCE->fifo8[0];
g_rx_len--;
}

Expand All @@ -90,9 +90,9 @@ void processSPI()

// Write any pending bytes out.
while (g_tx_buffer &&
(((SPI->dma & MXC_F_SPI_DMA_TX_LVL) >> MXC_F_SPI_DMA_TX_LVL_POS) < MXC_SPI_FIFO_DEPTH) &&
(((FASTSPI_INSTANCE->dma & MXC_F_SPI_DMA_TX_LVL) >> MXC_F_SPI_DMA_TX_LVL_POS) < MXC_SPI_FIFO_DEPTH) &&
g_tx_len > 0) {
SPI->fifo8[0] = *g_tx_buffer++;
FASTSPI_INSTANCE->fifo8[0] = *g_tx_buffer++;
g_tx_len--;
}

Expand All @@ -103,19 +103,19 @@ void processSPI()

void FastSPI_IRQHandler()
{
uint32_t status = SPI->intfl;
uint32_t status = FASTSPI_INSTANCE->intfl;

if (status & MXC_F_SPI_INTFL_MST_DONE) { // Master done (TX complete)
g_master_done = 1;
SPI->intfl |= MXC_F_SPI_INTFL_MST_DONE; // Clear flag
FASTSPI_INSTANCE->intfl |= MXC_F_SPI_INTFL_MST_DONE; // Clear flag
}

if (status & MXC_F_SPI_INTFL_RX_THD) {
SPI->intfl |= MXC_F_SPI_INTFL_RX_THD;
FASTSPI_INSTANCE->intfl |= MXC_F_SPI_INTFL_RX_THD;
}

if (status & MXC_F_SPI_INTFL_TX_THD) {
SPI->intfl |= MXC_F_SPI_INTFL_TX_THD;
FASTSPI_INSTANCE->intfl |= MXC_F_SPI_INTFL_TX_THD;
}
}

Expand Down Expand Up @@ -187,33 +187,33 @@ int spi_init()
fastspi_spi_pins.port->ds0 |= fastspi_spi_pins.mask;
fastspi_spi_pins.port->ds1 |= fastspi_spi_pins.mask;

SPI->ctrl0 =
FASTSPI_INSTANCE->ctrl0 =
(0b0100
<< MXC_F_SPI_CTRL0_SS_ACTIVE_POS) | // Set SSEL = SS2 <-- TODO(Jake): Improve this when other drivers are added
MXC_F_SPI_CTRL0_MST_MODE | // Select controller mode
MXC_F_SPI_CTRL0_EN; // Enable SPI

SPI->ctrl2 = (8 << MXC_F_SPI_CTRL2_NUMBITS_POS); // Set 8 bits per character
FASTSPI_INSTANCE->ctrl2 = (8 << MXC_F_SPI_CTRL2_NUMBITS_POS); // Set 8 bits per character

SPI->sstime =
FASTSPI_INSTANCE->sstime =
(1 << MXC_F_SPI_SSTIME_PRE_POS) | // Remove any delay time between SSEL and SCLK edges
(128 << MXC_F_SPI_SSTIME_POST_POS) | (1 << MXC_F_SPI_SSTIME_INACT_POS);

SPI->dma = MXC_F_SPI_DMA_TX_FIFO_EN | // Enable TX FIFO
FASTSPI_INSTANCE->dma = MXC_F_SPI_DMA_TX_FIFO_EN | // Enable TX FIFO
(31 << MXC_F_SPI_DMA_TX_THD_VAL_POS) | // Set TX threshold to 31
MXC_F_SPI_DMA_DMA_TX_EN; // Enable DMA for the TX FIFO

SPI->inten |= MXC_F_SPI_INTFL_MST_DONE; // Enable the "Transaction complete" interrupt
FASTSPI_INSTANCE->inten |= MXC_F_SPI_INTFL_MST_DONE; // Enable the "Transaction complete" interrupt

SPI->intfl = SPI->intfl; // Clear any any interrupt flags that may already be set
FASTSPI_INSTANCE->intfl = FASTSPI_INSTANCE->intfl; // Clear any any interrupt flags that may already be set

err = MXC_SPI_SetFrequency(SPI, SPI_SPEED);
err = MXC_SPI_SetFrequency(FASTSPI_INSTANCE, FASTSPI_SPEED);
if (err)
return err;

NVIC_EnableIRQ(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(SPI)));
MXC_NVIC_SetVector(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(SPI)), FastSPI_IRQHandler);
NVIC_SetPriority(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(SPI)), 0);
NVIC_EnableIRQ(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(FASTSPI_INSTANCE)));
MXC_NVIC_SetVector(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(FASTSPI_INSTANCE)), FastSPI_IRQHandler);
NVIC_SetPriority(MXC_SPI_GET_IRQ(MXC_SPI_GET_IDX(FASTSPI_INSTANCE)), 0);

err = _dma_init();

Expand All @@ -225,7 +225,7 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
g_tx_done = 0;
g_rx_done = 0;
g_master_done = 0;
mxc_spi_width_t width = MXC_SPI_GetWidth(SPI);
mxc_spi_width_t width = MXC_SPI_GetWidth(FASTSPI_INSTANCE);

// Set the number of bytes to transmit/receive for the SPI transaction
if (width == SPI_WIDTH_STANDARD) {
Expand All @@ -237,38 +237,38 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
dummy bytes must be transmitted to support half duplex.
*/
g_dummy_len = rxlen - txlen;
SPI->ctrl1 = ((txlen + g_dummy_len) << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS);
FASTSPI_INSTANCE->ctrl1 = ((txlen + g_dummy_len) << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS);
} else {
SPI->ctrl1 = txlen << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS;
FASTSPI_INSTANCE->ctrl1 = txlen << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS;
}
} else { // width != SPI_WIDTH_STANDARD
SPI->ctrl1 = (txlen << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS) |
FASTSPI_INSTANCE->ctrl1 = (txlen << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS) |
(rxlen << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS);
}

SPI->dma &= ~(MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN | MXC_F_SPI_DMA_RX_FIFO_EN |
FASTSPI_INSTANCE->dma &= ~(MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN | MXC_F_SPI_DMA_RX_FIFO_EN |
MXC_F_SPI_DMA_DMA_RX_EN); // Disable FIFOs before clearing as recommended by UG
SPI->dma |= (MXC_F_SPI_DMA_TX_FLUSH | MXC_F_SPI_DMA_RX_FLUSH); // Clear the FIFOs
FASTSPI_INSTANCE->dma |= (MXC_F_SPI_DMA_TX_FLUSH | MXC_F_SPI_DMA_RX_FLUSH); // Clear the FIFOs

// TX
if (txlen > 1) {
// Configure TX DMA channel to fill the SPI TX FIFO
SPI->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN |
FASTSPI_INSTANCE->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN |
(31 << MXC_F_SPI_DMA_TX_THD_VAL_POS));
SPI->fifo8[0] = src[0];
FASTSPI_INSTANCE->fifo8[0] = src[0];
// ^ Hardware requires writing the first byte into the FIFO manually.
MXC_DMA->ch[g_tx_channel].src = (uint32_t)(src + 1);
MXC_DMA->ch[g_tx_channel].cnt = txlen - 1;
MXC_DMA->ch[g_tx_channel].ctrl |= MXC_F_DMA_CTRL_SRCINC;
MXC_DMA->ch[g_tx_channel].ctrl |= MXC_F_DMA_CTRL_EN; // Start the DMA
} else if (txlen == 1) {
// Workaround for single-length transactions not triggering CTZ
SPI->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN);
SPI->fifo8[0] = src[0]; // Write first byte into FIFO
FASTSPI_INSTANCE->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN);
FASTSPI_INSTANCE->fifo8[0] = src[0]; // Write first byte into FIFO
g_tx_done = 1;
} else if (txlen == 0 && width == SPI_WIDTH_STANDARD) {
// Configure TX DMA channel to retransmit a dummy byte
SPI->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN);
FASTSPI_INSTANCE->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN);
MXC_DMA->ch[g_tx_channel].src = (uint32_t)&g_dummy_byte;
MXC_DMA->ch[g_tx_channel].cnt = rxlen;
MXC_DMA->ch[g_tx_channel].ctrl &= ~MXC_F_DMA_CTRL_SRCINC;
Expand All @@ -278,14 +278,14 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
// RX
if (rxlen > 0) {
// Configure RX DMA channel to unload the SPI RX FIFO
SPI->dma |= (MXC_F_SPI_DMA_RX_FIFO_EN | MXC_F_SPI_DMA_DMA_RX_EN);
FASTSPI_INSTANCE->dma |= (MXC_F_SPI_DMA_RX_FIFO_EN | MXC_F_SPI_DMA_DMA_RX_EN);
MXC_DMA->ch[g_rx_channel].dst = (uint32_t)dest;
MXC_DMA->ch[g_rx_channel].cnt = rxlen;
MXC_DMA->ch[g_rx_channel].ctrl |= MXC_F_DMA_CTRL_EN; // Start the DMA
}

// Start the SPI transaction
SPI->ctrl0 |= MXC_F_SPI_CTRL0_START;
FASTSPI_INSTANCE->ctrl0 |= MXC_F_SPI_CTRL0_START;

/*
Handle slave-select (SS) deassertion. This must be done AFTER launching the transaction
Expand All @@ -297,9 +297,9 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
on the value of CTRL->SS_CTRL, which causes the glitch.
*/
if (deassert)
SPI->ctrl0 &= ~MXC_F_SPI_CTRL0_SS_CTRL;
FASTSPI_INSTANCE->ctrl0 &= ~MXC_F_SPI_CTRL0_SS_CTRL;
else
SPI->ctrl0 |= MXC_F_SPI_CTRL0_SS_CTRL;
FASTSPI_INSTANCE->ctrl0 |= MXC_F_SPI_CTRL0_SS_CTRL;

// Wait for the transaction to complete.
while (!((g_tx_done && g_master_done) && (src != NULL && txlen > 0)) &&
Expand All @@ -309,7 +309,7 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
This is especially common with extremely short transactions, where all 3
interrupts may fire almost simultaneously.
*/
if ((src != NULL && txlen > 0) && SPI->intfl & MXC_F_SPI_INTFL_MST_DONE)
if ((src != NULL && txlen > 0) && FASTSPI_INSTANCE->intfl & MXC_F_SPI_INTFL_MST_DONE)
g_master_done = 1;
if ((src != NULL && txlen > 0) &&
MXC_DMA->ch[g_tx_channel].status & MXC_F_DMA_STATUS_CTZ_IF)
Expand All @@ -324,10 +324,10 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo

int spi_exit_quadmode()
{
return MXC_SPI_SetWidth(SPI, SPI_WIDTH_STANDARD);
return MXC_SPI_SetWidth(FASTSPI_INSTANCE, SPI_WIDTH_STANDARD);
}

int spi_enter_quadmode()
{
return MXC_SPI_SetWidth(SPI, SPI_WIDTH_QUAD);
return MXC_SPI_SetWidth(FASTSPI_INSTANCE, SPI_WIDTH_QUAD);
}
16 changes: 8 additions & 8 deletions Libraries/MiscDrivers/SRAM/fastspi.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,12 +27,12 @@
// NOTE: "fastspi_config.h should be implemented for each Board Support Package and placed in
// its include folder in Libraries/Boards

#ifndef SPI
#error Missing fastspi_config.h definition 'SPI' to select SPI instance
#ifndef FASTSPI_INSTANCE
#error Missing fastspi_config.h definition 'FASTSPI_INSTANCE' to select SPI instance
#endif

#ifndef SPI_SPEED
#error Missing fastspi_config.h definition 'SPI_SPEED' to set SPI clock frequency
#ifndef FASTSPI_SPEED
#error Missing fastspi_config.h definition 'FASTSPI_SPEED' to set SPI clock frequency
#endif

// These pin definitions should also be provided in the "fastspi_config.h" file
Expand All @@ -48,7 +48,7 @@ extern const mxc_gpio_cfg_t fastspi_spi_pins;
* @return An integer status code. 0 indicates success, while a non-zero value
* indicates an error during initialization.
*/
extern int spi_init();
int spi_init();

/**
* @brief Transmits and receives data using the SPI module.
Expand All @@ -68,7 +68,7 @@ extern int spi_init();
* @return An integer status code. 0 indicates success, while a non-zero value
* indicates an error during the SPI transaction.
*/
extern int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bool deassert);
int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bool deassert);

/**
* @brief Exits the quad mode for SPI (Serial Peripheral Interface) communication.
Expand All @@ -80,7 +80,7 @@ extern int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rx
* @return An integer status code. 0 indicates success, while a non-zero value
* indicates an error during the quad mode exit process.
*/
extern int spi_exit_quadmode();
int spi_exit_quadmode();

/**
* @brief Enters the quad mode for SPI (Serial Peripheral Interface) communication.
Expand All @@ -92,6 +92,6 @@ extern int spi_exit_quadmode();
* @return An integer status code. 0 indicates success, while a non-zero value
* indicates an error during the quad mode entry process.
*/
extern int spi_enter_quadmode();
int spi_enter_quadmode();

#endif // LIBRARIES_MISCDRIVERS_SRAM_FASTSPI_H_

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