clang-format

Examples/MAX78000/FTHR_SRAM/main.c

@@ -59,7 +59,12 @@
 
 /***** Globals *****/
 int g_sw_overhead = 0;
-#define TIME(x, output) {MXC_TMR_SW_Start(MXC_TMR0);(x);(elapsed) = MXC_TMR_SW_Stop(MXC_TMR0) - g_sw_overhead;}
+#define TIME(x, output)                                        \
+    {                                                          \
+        MXC_TMR_SW_Start(MXC_TMR0);                            \
+        (x);                                                   \
+        (elapsed) = MXC_TMR_SW_Stop(MXC_TMR0) - g_sw_overhead; \
+    }
 
 /***** Functions *****/
 
@@ -92,10 +97,7 @@ int main(void)
     g_sw_overhead = MXC_TMR_SW_Stop(MXC_TMR0);
 
     // Benchmark internal memory write
-    TIME(
-        memset(tx_buffer, 0, TEST_SIZE),
-        elapsed
-    );
+    TIME(memset(tx_buffer, 0, TEST_SIZE), elapsed);
     printf("(Benchmark) Wrote %i bytes to internal SRAM in %ius\n", TEST_SIZE, elapsed);
 
     // Initialize test pattern
@@ -114,18 +116,14 @@ int main(void)
     // =====================================================
     // Standard SPI
     printf("Test 1: Standard SPI write...\n");
-    TIME(
-        N01S830HA_write(TEST_ADDR, tx_buffer, TEST_SIZE), // SRAM Write
-        elapsed
-    );
+    TIME(N01S830HA_write(TEST_ADDR, tx_buffer, TEST_SIZE), // SRAM Write
+         elapsed);
     printf("\tDone (%i bytes in %ius)\n", TEST_SIZE, elapsed);
 
     // Read and validate
     printf("Test 2: Standard SPI read...\n");
-    TIME(
-        N01S830HA_read(TEST_ADDR, rx_buffer, TEST_SIZE), // SRAM Read
-        elapsed
-    )
+    TIME(N01S830HA_read(TEST_ADDR, rx_buffer, TEST_SIZE), // SRAM Read
+         elapsed)
     printf("\tRead finished (%i bytes in %ius)\n", TEST_SIZE, elapsed);
     printf("\tChecking for mismatches...\n");
     if (!validate(rx_buffer, tx_buffer, TEST_SIZE)) {
@@ -145,19 +143,15 @@ int main(void)
     printf("Test 3: QSPI write...\n");
 
     N01S830HA_enter_quadmode(); // Enter quad mode
-
-    TIME(
-        N01S830HA_write(TEST_ADDR, tx_buffer, TEST_SIZE), // SRAM Write
-        elapsed
-    );
+
+    TIME(N01S830HA_write(TEST_ADDR, tx_buffer, TEST_SIZE), // SRAM Write
+         elapsed);
     printf("\tDone (%i bytes in %ius)\n", TEST_SIZE, elapsed);
 
     // Read and validate
     printf("Test 4: QSPI read...\n");
-    TIME(
-        N01S830HA_read(TEST_ADDR, rx_buffer, TEST_SIZE), // SRAM Read
-        elapsed
-    )
+    TIME(N01S830HA_read(TEST_ADDR, rx_buffer, TEST_SIZE), // SRAM Read
+         elapsed)
     printf("\tRead finished (%i bytes in %ius)\n", TEST_SIZE, elapsed);
     printf("\tChecking for mismatches...\n");
     if (!validate(rx_buffer, tx_buffer, TEST_SIZE)) {

Libraries/MiscDrivers/SRAM/N01S830HA.c

@@ -49,7 +49,10 @@ MODE_t g_current_mode;
 int _g_err = E_NO_ERROR;
 // Error checking macro that can be used inside functions with an 'int' return
 // type
-#define ERR_CHECK(x) if ((_g_err = (x)) != E_NO_ERROR) { return (_g_err); }
+#define ERR_CHECK(x)                    \
+    if ((_g_err = (x)) != E_NO_ERROR) { \
+        return (_g_err);                \
+    }
 
 // =============================================================================
 
@@ -79,17 +82,17 @@ int N01S830HA_init()
     ERR_CHECK(N01S830HA_exit_quadmode()); // Protect against quad-mode lock-up
 
     // The first thing we need to do is disable the HOLD function, which
-    // is enabled by default.  There is a hardware (hold pin) and software 
+    // is enabled by default.  There is a hardware (hold pin) and software
     // (hold bit) component to this.
-    
+
     // Set the hold pin to the HIGH state.
     ERR_CHECK(MXC_GPIO_Config(&N01S830HA_hold_pin));
     MXC_GPIO_OutSet(N01S830HA_hold_pin.port, N01S830HA_hold_pin.mask);
 
     ERR_CHECK(N01S830HA_write_mode_reg(0b1)); // Disable hold function
 
     // Now, validate that we were able to write to the mode register
-    // This is the closest thing we have to a "read id" or 
+    // This is the closest thing we have to a "read id" or
     // communication verification for this SRAM chip.
     uint8_t mode_reg;
     ERR_CHECK(N01S830HA_read_mode_reg(&mode_reg));
@@ -138,7 +141,8 @@ int N01S830HA_enter_quadmode()
     return E_NO_ERROR;
 }
 
-int N01S830HA_exit_quadmode() {
+int N01S830HA_exit_quadmode()
+{
     uint8_t tx_data = CMD_RESET_IO;
 
     ERR_CHECK(spi_enter_quadmode());
@@ -175,11 +179,12 @@ int N01S830HA_write_mode_reg(uint8_t val)
 {
     uint8_t data[2] = { CMD_WRITE_MODE_REG, val };
     ERR_CHECK(spi_transmit(data, 2, NULL, 0, true));
-    MXC_Delay(MXC_DELAY_USEC(100)); // Some small delay after updating the mode reg appears to be necessary.
+    MXC_Delay(MXC_DELAY_USEC(
+        100)); // Some small delay after updating the mode reg appears to be necessary.
     return E_NO_ERROR;
 }
 
-int N01S830HA_read_mode_reg(uint8_t* out)
+int N01S830HA_read_mode_reg(uint8_t *out)
 {
     uint8_t cmd = CMD_READ_MODE_REG;
     ERR_CHECK(spi_transmit(&cmd, 1, NULL, 0, false));

Libraries/MiscDrivers/SRAM/N01S830HA.h

@@ -55,7 +55,7 @@ extern const mxc_gpio_cfg_t N01S830HA_hold_pin;
 
 // =======================================================================================
 
-// SPI TRANSPORT LAYER 
+// SPI TRANSPORT LAYER
 // - Must be implemented externally (!)
 
 /**
@@ -186,6 +186,6 @@ int N01S830HA_write_mode_reg(uint8_t val);
  *
  * @return 0 on success, or an error code on failure.
  */
-int N01S830HA_read_mode_reg(uint8_t* out);
+int N01S830HA_read_mode_reg(uint8_t *out);
 
 #endif // EXAMPLES_MAX78000_QSPI_N01S830HA_H_

Libraries/MiscDrivers/SRAM/N01S830HA_config.h

@@ -25,10 +25,10 @@
 // the port, pin, and vssel definitions above.
 
 static const mxc_gpio_cfg_t N01S830HA_hold_pin = { .port = N01S830HA_HOLD_PIN_PORT,
-                                           .mask = N01S830HA_HOLD_PIN_MASK,
-                                           .func = MXC_GPIO_FUNC_OUT,
-                                           .pad = MXC_GPIO_PAD_WEAK_PULL_UP,
-                                           .vssel = N01S830HA_VSSEL };
+                                                   .mask = N01S830HA_HOLD_PIN_MASK,
+                                                   .func = MXC_GPIO_FUNC_OUT,
+                                                   .pad = MXC_GPIO_PAD_WEAK_PULL_UP,
+                                                   .vssel = N01S830HA_VSSEL };
 #endif
 
 #endif // N01S830HA_CONFIG_H

Libraries/MiscDrivers/SRAM/fastspi.c

@@ -55,12 +55,11 @@ uint8_t *g_tx_buffer;
 uint32_t g_rx_len;
 uint32_t g_tx_len;
 
-// Polling flags the application code can optionally 
+// Polling flags the application code can optionally
 static volatile bool g_tx_done = 0;
 static volatile bool g_rx_done = 0;
 static volatile bool g_master_done = 0;
 
-
 void DMA_TX_IRQHandler()
 {
     volatile mxc_dma_ch_regs_t *ch =
@@ -204,9 +203,11 @@ int spi_init()
     fastspi_spi_pins.port->ds0 |= fastspi_spi_pins.mask;
     fastspi_spi_pins.port->ds1 |= fastspi_spi_pins.mask;
 
-    SPI->ctrl0 = (0b0100 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) | // Set SSEL = SS2 <-- TODO(Jake): Improve this when other drivers are added
-                 MXC_F_SPI_CTRL0_MST_MODE | // Select controller mode
-                 MXC_F_SPI_CTRL0_EN; // Enable SPI
+    SPI->ctrl0 =
+        (0b0100
+         << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) | // Set SSEL = SS2 <-- TODO(Jake): Improve this when other drivers are added
+        MXC_F_SPI_CTRL0_MST_MODE | // Select controller mode
+        MXC_F_SPI_CTRL0_EN; // Enable SPI
 
     SPI->ctrl2 = (8 << MXC_F_SPI_CTRL2_NUMBITS_POS); // Set 8 bits per character
 
@@ -269,7 +270,7 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
     if (txlen > 1) {
         // Configure TX DMA channel to fill the SPI TX FIFO
         SPI->dma |= (MXC_F_SPI_DMA_TX_FIFO_EN | MXC_F_SPI_DMA_DMA_TX_EN |
-                        (31 << MXC_F_SPI_DMA_TX_THD_VAL_POS));
+                     (31 << MXC_F_SPI_DMA_TX_THD_VAL_POS));
         SPI->fifo8[0] = src[0];
         // ^ Hardware requires writing the first byte into the FIFO manually.
         MXC_DMA->ch[g_tx_channel].src = (uint32_t)(src + 1);
@@ -318,7 +319,7 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
 
     // Wait for the transaction to complete.
     while (!((g_tx_done && g_master_done) && (src != NULL && txlen > 0)) &&
-            !(g_rx_done && (dest != NULL && rxlen > 0))) {
+           !(g_rx_done && (dest != NULL && rxlen > 0))) {
         /*
         The following polling is a safety fallback to catch any missed interrupts.
         This is especially common with extremely short transactions, where all 3 
@@ -337,7 +338,7 @@ int spi_transmit(uint8_t *src, uint32_t txlen, uint8_t *dest, uint32_t rxlen, bo
     return E_SUCCESS;
 }
 
-int spi_exit_quadmode() 
+int spi_exit_quadmode()
 {
     return MXC_SPI_SetWidth(SPI, SPI_WIDTH_STANDARD);
 }

Libraries/MiscDrivers/SRAM/fastspi.h

@@ -38,11 +38,11 @@
  * @brief   "fast" and optimized DMA SPI drivers for use alongside external SRAM drivers
  */
 
-#include "fastspi_config.h" 
+#include "fastspi_config.h"
 // NOTE: "fastspi_config.h should be implemented for each Board Support Package and placed in
 //       its include folder in Libraries/Boards
 
-#ifndef SPI 
+#ifndef SPI
 #error Missing fastspi_config.h definition 'SPI' to select SPI instance
 #endif