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@Csomi Csomi released this 18 Mar 11:32
2015_r2
2524f19

Change log:

  1. The supported tools version for this release are :
  2. Library changes :
    • AXI_JESD_GT core has changed to support per lane control to allow asymmetrical transmit and receive lane sharing.
    • ALL core parameter names made consistent and follow the new naming convention
    • Added DAC FIFO, this core allows to store custom DAC samples from memory, and play back at full rate
    • IPs for Altera have updated interfaces for easier connectivity in QSYS
    • AXI_DMAC auto-detects asynchronous clock configuration
  3. Project changes :
    • Added CPACK / UPACK to FMCOMMS1, FMCOMMS5, FMCOMMS6, MOTCON2_FMC projects
    • FMCOMMS2: ARRADIO added (replaces C5SOC)
    • DAQ2: Added DAC FIFO
  4. New projects :
    • PicozedSDR (ccfmc/ccbrk/ccpci)
    • DAQ2 for A10GX
    • DAQ2 KCU105 support
    • DAQ3 ZC706
  5. Unsupported or in development projects (do NOT use)
    • DAQ1 ZC706
    • FMCJESDADC1 A5SOC
    • USDRX1 A5GT and ZC706
    • USB-FX3 ZC706
    • CFTL_CIP and CFTL_STD
    • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)
    • FMCADC5 VC707
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