Change log:

1. Supported tools version for this release are:
   • Vivado 2016.2
   • Quartus 16.0
2. Major updates:
   • IP cores that are specific to FPGA devices are moved into their own respective folders (altera/xilinx)
   • The JESD transceiver frame work has changed. The IP cores now support asymmetrical lane sharing across transmit and receive links while supporting dynamic reconfiguration. The Xilinx projects, the ADI transceiver cores may now be replaced with Xilinx JESD PHY IP at the expense of Eye Scan function.
   • The AD9361 IP core for Altera supports 1R1T mode as well as separate clock, receive and transmit primitives. The core supports both Cyclone V and Arria 10 devices.
   • Additional features added to axi_ad9361 IP core:
     • CMOS support
     • New parameters for finer data path configuration
     • TDD support, with optional ENABLE/TXNRX pin control by software.
   • Altera support for axi_ad9152
   • Add xilinx/axi_dacfifo for high speed DAC paths
3. Library changes:
   • Added new IP cores:
     • util_adxcvr
     • avl_adxcvr
     • axi_adxcvr
     • axi_ad9684
     • axi_ad9162
     • axi_ad7616
   • Removed obsolete and unsupported cores:
     • util_jesd_gt
     • util_gtlb
     • axi_jesd_gt
4. Project changes:
   • Supports Arria 10 SOC, Zynq MP SOC Ultrascale+ devices
   • DAQ1: add CPLD logic and new ADC core (axi_ad9684)
   • PZSDR moved to PZSDR2
   • FMCOMMS2: add support for A10GX and ZCU102
   • Removed obsolete and unsupported projects
     • FMCOMMS6
   • New projects:
     • ADRV9371X
     • FMCOMMS11
     • PZSDR1
     • PLUTO
     • USRPE31X
5. Unsupported or in development projects (do NOT use):
   • The FMCOMMS2 projects on Arria 10 devices is provided as a template ONLY. The project will NOT work on hardware (A10GX or A10SOC) due to Altera's lack of knowledge on their device bank/FMC pin assignments.
   • CFTL_CIP and CFTL_STD
   • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)

Change log:

1. Supported tools version for this release are :
   • Vivado 2015.4.2 - KCU105 projects requires some patches see bellow
   • Quartus 15.1
2. Library changes :
   • fix data clipping for AXI_HDMI_TX
   • patch for UTIL_DACFIFO
3. Project changes: None
4. New projects:
   • AD7768EVB

Note: The project using the KCU105 carrier requires the following patches

The setup we use is listed below, you may change it to suit your needs.

AR66031

1. Download the zip file from www.xilinx.com/support/answers/66031.html
2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66031
3. unzip ~/Downloads/AR66031_Vivado_2015_4_preliminary_rev66031.zip
   -d /opt/Xilinx/Vivado/2015.4/KCU105/AR66031/
4. export MYVIVADO=/opt/Xilinx/Vivado/2015.4/KCU105/AR66031/vivado

AR66052

1. Download the verilog file from www.xilinx.com/support/answers/66052.html
2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66052
3. cp ~/Downloads/gig_ethernet_pcs_pma_1_serdes_1_to_10_ser8.v
   /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v
4. sed -i 's/gig_ethernet_pcs_pma_1/bd_0_pcs_pma_0/g'
   /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v

Change log:

1. The supported tools version for this release are :
   • Vivado 2015.2.1
   • Quartus 15.1
2. Library changes :
   • AXI_JESD_GT core has changed to support per lane control to allow asymmetrical transmit and receive lane sharing.
   • ALL core parameter names made consistent and follow the new naming convention
   • Added DAC FIFO, this core allows to store custom DAC samples from memory, and play back at full rate
   • IPs for Altera have updated interfaces for easier connectivity in QSYS
   • AXI_DMAC auto-detects asynchronous clock configuration
3. Project changes :
   • Added CPACK / UPACK to FMCOMMS1, FMCOMMS5, FMCOMMS6, MOTCON2_FMC projects
   • FMCOMMS2: ARRADIO added (replaces C5SOC)
   • DAQ2: Added DAC FIFO
4. New projects :
   • PicozedSDR (ccfmc/ccbrk/ccpci)
   • DAQ2 for A10GX
   • DAQ2 KCU105 support
   • DAQ3 ZC706
5. Unsupported or in development projects (do NOT use)
   • DAQ1 ZC706
   • FMCJESDADC1 A5SOC
   • USDRX1 A5GT and ZC706
   • USB-FX3 ZC706
   • CFTL_CIP and CFTL_STD
   • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)
   • FMCADC5 VC707

Supported tools:

• Vivado 2014.4.1
• Quartus 15.0

Supported tools:

• Vivado 2014.2
• Quartus 14.0

Supported tools:

• Vivado 2013.4
• Quartus 14.0