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Add Cache Coherency support on Ultrascale projects #1527

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14 changes: 10 additions & 4 deletions projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,10 @@ if {![info exists ADI_PHY_SEL]} {
set ADI_PHY_SEL 1
}

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
Expand Down Expand Up @@ -316,6 +320,7 @@ if {$INTF_CFG != "TX"} {
} else {
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)]
}
ad_ip_parameter axi_mxfe_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
}

# Instantiate DAC (Tx) path
Expand Down Expand Up @@ -384,6 +389,7 @@ if {$INTF_CFG != "RX"} {
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)]
}
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
ad_ip_parameter axi_mxfe_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
}

if {$ADI_PHY_SEL == 1} {
Expand Down Expand Up @@ -490,8 +496,8 @@ if {$INTF_CFG != "TX"} {
if {$ADI_PHY_SEL == 1} {
ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi
}
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi $CACHE_COHERENCY

# Interrupts
ad_cpu_interrupt ps-13 mb-12 axi_mxfe_rx_dma/irq
Expand Down Expand Up @@ -541,8 +547,8 @@ if {$INTF_CFG != "RX"} {
ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
# GT / ADC
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi $CACHE_COHERENCY

# Interrupts
ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
Expand Down
9 changes: 7 additions & 2 deletions projects/ad9083_evb/common/ad9083_evb_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl

# RX parameters
Expand Down Expand Up @@ -57,6 +61,7 @@ ad_ip_instance axi_dmac axi_ad9083_rx_dma [list \
DMA_LENGTH_WIDTH 31 \
DMA_DATA_WIDTH_DEST 128 \
DMA_DATA_WIDTH_SRC $adc_dma_data_width \
CACHE_COHERENT $CACHE_COHERENCY \
]

# common cores
Expand Down Expand Up @@ -171,8 +176,8 @@ ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9083_rx_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi $CACHE_COHERENCY

# interrupts

Expand Down
9 changes: 7 additions & 2 deletions projects/ad9656_fmc/common/ad9656_fmc_bd.tcl
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# RX parameters
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 4 ; # M
Expand Down Expand Up @@ -48,6 +52,7 @@ ad_ip_instance axi_dmac axi_ad9656_rx_dma [list \
AXI_SLICE_SRC false \
DMA_DATA_WIDTH_DEST 128 \
FIFO_SIZE 32 \
CACHE_COHERENT $CACHE_COHERENCY \
]

# common cores
Expand Down Expand Up @@ -115,8 +120,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9656_rx_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi $CACHE_COHERENCY

# interrupts

Expand Down
9 changes: 7 additions & 2 deletions projects/ad9694_fmc/common/ad9694_fmc_bd.tcl
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
Expand Down Expand Up @@ -62,6 +66,7 @@ ad_ip_instance axi_dmac axi_ad9694_rx_dma [list \
DMA_LENGTH_WIDTH 24 \
DMA_DATA_WIDTH_DEST 128 \
DMA_DATA_WIDTH_SRC $adc_dma_data_width \
CACHE_COHERENT $CACHE_COHERENCY \
]

# common cores
Expand Down Expand Up @@ -168,8 +173,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9694_rx_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi $CACHE_COHERENCY

# interrupts

Expand Down
9 changes: 7 additions & 2 deletions projects/ad9695_fmc/common/ad9695_fmc_bd.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
Expand Down Expand Up @@ -62,6 +66,7 @@ ad_ip_instance axi_dmac axi_ad9695_rx_dma [list \
DMA_LENGTH_WIDTH 24 \
DMA_DATA_WIDTH_DEST 128 \
DMA_DATA_WIDTH_SRC $adc_dma_data_width \
CACHE_COHERENT $CACHE_COHERENCY \
]

# common cores
Expand Down Expand Up @@ -159,8 +164,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9695_rx_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi $CACHE_COHERENCY

# interrupts

Expand Down
11 changes: 8 additions & 3 deletions projects/ad9783_ebz/common/ad9783_ebz_bd.tcl
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Original file line number Diff line number Diff line change
@@ -1,8 +1,12 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# dac interface

create_bd_port -dir O dci_p
Expand All @@ -27,6 +31,7 @@ ad_ip_parameter axi_ad9783_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9783_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1
ad_ip_parameter axi_ad9783_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

# dac-path channel upack

Expand Down Expand Up @@ -66,8 +71,8 @@ ad_cpu_interconnect 0x7c420000 axi_ad9783_dma

# interconnect (mem/dac)

ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi $CACHE_COHERENCY
ad_connect $sys_dma_resetn axi_ad9783_dma/m_src_axi_aresetn

# interrupts
Expand Down
11 changes: 8 additions & 3 deletions projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl
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Original file line number Diff line number Diff line change
@@ -1,10 +1,14 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# interfaces and IO ports

create_bd_port -dir I spi_vco_csn_i
Expand Down Expand Up @@ -57,6 +61,7 @@ ad_ip_instance axi_dmac ad9694_dma [list \
DMA_DATA_WIDTH_DEST 64 \
SYNC_TRANSFER_START 1 \
FIFO_SIZE 32 \
CACHE_COHERENT $CACHE_COHERENCY \
]

# 3-wire SPI for clock synthesizer & VCO - 12.5MHz SCLK rate
Expand Down Expand Up @@ -199,8 +204,8 @@ ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9694_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi $CACHE_COHERENCY

# interrupts

Expand Down
18 changes: 13 additions & 5 deletions projects/adrv9001/common/adrv9001_bd.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
### SPDX short identifier: ADIBSD
###############################################################################

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

# create debug ports
create_bd_port -dir O adc1_div_clk
create_bd_port -dir O adc2_div_clk
Expand Down Expand Up @@ -85,6 +89,7 @@ ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

ad_ip_instance util_cpack2 util_adc_1_pack { \
NUM_OF_CHANNELS 4 \
Expand All @@ -102,6 +107,7 @@ ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

ad_ip_instance util_cpack2 util_adc_2_pack { \
NUM_OF_CHANNELS 2 \
Expand All @@ -119,6 +125,7 @@ ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

ad_ip_instance util_upack2 util_dac_1_upack { \
NUM_OF_CHANNELS 4 \
Expand All @@ -136,6 +143,7 @@ ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

ad_ip_instance util_upack2 util_dac_2_upack { \
NUM_OF_CHANNELS 2 \
Expand Down Expand Up @@ -282,11 +290,11 @@ ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma

# memory inteconnect

ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi $CACHE_COHERENCY

ad_connect $sys_cpu_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn
Expand Down
19 changes: 13 additions & 6 deletions projects/adrv9009/common/adrv9009_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,10 @@
# [TX/RX/RX_OS]_JESD_S : Number of samples per frame
# [TX/RX/RX_OS]_JESD_NP : Number of bits per sample

if {![info exists CACHE_COHERENCY]} {
set CACHE_COHERENCY false
}

set MAX_TX_NUM_OF_LANES 4
set MAX_RX_NUM_OF_LANES 2
set MAX_RX_OS_NUM_OF_LANES 2
Expand Down Expand Up @@ -109,6 +113,7 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width

Expand Down Expand Up @@ -161,6 +166,7 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_widt
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC true
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

# adc-os peripherals

Expand Down Expand Up @@ -206,6 +212,7 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SA
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC true
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY

# common cores

Expand Down Expand Up @@ -453,12 +460,12 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_rx_os_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY
ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi $CACHE_COHERENCY
ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY
ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi $CACHE_COHERENCY

# interrupts

Expand Down
13 changes: 10 additions & 3 deletions projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -29,6 +29,9 @@ ad_ip_parameter i2s_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 0
ad_ip_parameter i2s_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 32
ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter i2s_tx_dma CONFIG.CACHE_COHERENT 1
ad_ip_parameter i2s_tx_dma CONFIG.AXI_AXCACHE 0b1111
ad_ip_parameter i2s_tx_dma CONFIG.AXI_AXPROT 0b010

ad_ip_instance axi_dmac i2s_rx_dma
ad_ip_parameter i2s_rx_dma CONFIG.DMA_TYPE_SRC 1
Expand All @@ -42,6 +45,9 @@ ad_ip_parameter i2s_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 0
ad_ip_parameter i2s_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter i2s_rx_dma CONFIG.CACHE_COHERENT 1
ad_ip_parameter i2s_rx_dma CONFIG.AXI_AXCACHE 0b1111
ad_ip_parameter i2s_rx_dma CONFIG.AXI_AXPROT 0b010

# i2s connections

Expand Down Expand Up @@ -95,8 +101,9 @@ ad_cpu_interconnect 0x41000000 i2s_rx_dma
ad_cpu_interconnect 0x41001000 i2s_tx_dma
ad_cpu_interconnect 0x42000000 axi_i2s_adi

ad_mem_hp0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi
ad_mem_hp0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi
ad_mem_hpc0_interconnect sys_cpu_clk sys_ps8/S_AXI_HPC0
ad_mem_hpc0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi
ad_mem_hpc0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi

# interrupts

Expand Down
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