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AD7405: Add AXI ADC support #1522

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AD7405: Add AXI ADC support #1522

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PIoandan
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@PIoandan PIoandan commented Nov 20, 2024 •
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PR Description

Add AXI ADC support to existing AD7405 project.
Update AD7405 project to account for the changes.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@PIoandan
library/ad7405: Add AXI ADC for ad7405 v1
f372fd6 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
projects/ad7405: Add cpack core and remove filter_reset port
e4b1a4d 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
library/ad7405: Fix ip connections
fb34d03 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
library/ad7405: Functional changes
593569a 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
projects/ad7405: Functional changes
eacf2bc 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
library/ad7405: Remove unnecessary ports
cf3c33b 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
projects/ad7405: Remove cpack core
470df3f 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan
library/ad7405: Clean ad7405 library
9b3c513 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan PIoandan marked this pull request as draft November 20, 2024 14:14
PIoandan and others added 2 commits December 13, 2024 14:04
@PIoandan
projects/ad7405: Set axi_clkgen to 40MHz/Add constraints
2a27a59 
Signed-off-by: Pop Ioan Daniel <[email protected]>
@sarpadi
util_dec256sinc24b: Updated module
3294cb2 
Compied HDL from ad7405 datasheet. Rearanged code and renamed module
Updated axi_ad7405 module instantation

Signed-off-by: sarpadi <[email protected]>
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@PopPaul2021 PopPaul2021 Awaiting requested review from PopPaul2021 PopPaul2021 is a code owner

@acostina acostina Awaiting requested review from acostina acostina is a code owner

@AndreiGrozav AndreiGrozav Awaiting requested review from AndreiGrozav AndreiGrozav is a code owner

@gastmaier gastmaier Awaiting requested review from gastmaier gastmaier is a code owner

@sarpadi sarpadi Awaiting requested review from sarpadi sarpadi is a code owner

@IuliaCMoldovan IuliaCMoldovan Awaiting requested review from IuliaCMoldovan IuliaCMoldovan will be requested when the pull request is marked ready for review IuliaCMoldovan is a code owner

@StancaPop StancaPop Awaiting requested review from StancaPop StancaPop will be requested when the pull request is marked ready for review StancaPop is a code owner

@LBFFilho LBFFilho Awaiting requested review from LBFFilho LBFFilho will be requested when the pull request is marked ready for review LBFFilho is a code owner

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2 participants
@PIoandan @sarpadi