docs: Fixes and cleanup

docs/library/axi_ad9144/index.rst

@@ -4,15 +4,17 @@ AXI AD9144 (OBSOLETE)
 ================================================================================
 
 .. warning::
-   This IP is was discontinued, limited support available. Last release for this
-   IP is ``hdl_2019_r2`` and can be found on our HDL repository, on the branch
-   with the same name.
+
+   The support for :git-hdl:`AXI AD9144 <hdl_2019_r2:library/axi_ad9144>`
+   has been discontinued, the latest tested release being ``hdl_2019_r2``.
+   This page is for legacy purposes only.
 
 The :git-hdl:`AXI AD9144 <hdl_2019_r2:library/axi_ad9144>` IP core can be used
 to interface the :adi:`AD9144` DAC. An AXI Memory Map interface is used for
-configuration. Data is sent in a format that can be transmitted by Xilinx's
-JESD IP. More about the generic framework interfacing DACs, can be read
-in :ref:`axi_adc`.
+configuration. Data is sent in a format that can be transmitted by AMD Xilinx's
+JESD IP.
+
+More about the generic framework interfacing DACs, can be read in :ref:`axi_adc`.
 
 Features
 --------------------------------------------------------------------------------
@@ -40,7 +42,6 @@ Files
    * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144_constr.xdc`
      - Constraint file of the IP.
 
-
 Block Diagram
 --------------------------------------------------------------------------------
 
@@ -160,9 +161,9 @@ Software Support
 
   * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/adi-ad9144-fmc-ebz.dtsi`
   * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9144-fmc-ebz.dts`
-  
+
 * No-OS device driver at:
-  
+
   * :git-no-os:`2019_r2:drivers/dac/ad9144/ad9144.c`
   * :git-no-os:`2019_r2:drivers/dac/ad9144/iio_ad9144.c`
 

docs/library/axi_ad9371/index.rst

@@ -4,9 +4,10 @@ AXI AD9371 (OBSOLETE)
 ================================================================================
 
 .. warning::
-   This IP is was discontinued, limited support available. Last release for this
-   IP is ``hdl_2019_r2`` and can be found on our HDL repository, on the branch
-   with the same name.
+
+   The support for :git-hdl:`AXI AD9371 <hdl_2019_r2:library/axi_ad9371>`
+   has been discontinued, the latest tested release being ``hdl_2019_r2``.
+   This page is for legacy purposes only.
 
 .. note::
    This page has a great historical background. The same functionalities are
@@ -15,7 +16,9 @@ AXI AD9371 (OBSOLETE)
 The :git-hdl:`AXI AD9371 <hdl_2019_r2:library/axi_ad9371>` IP core can be used
 to interface the :adi:`AD9371` device. An AXI Memory Map interface is used for
 configuration. Data is sent in a format that can be transmitted by Xilinx's
-JESD IP. More about the generic framework interfacing ADCs, that contains the
+JESD IP.
+
+More about the generic framework interfacing ADCs and DACs, that contains the
 ``up_dac_channel``, ``up_adc_channel`` and ``up_dac_common modules``,
 ``up_adc_common modules`` can be read in :ref:`axi_dac` and :ref:`axi_adc`.
 
@@ -174,7 +177,7 @@ The axi_ad9371 cores architecture contains:
 
   * ADC channel processing modules, one for each channel
     (receive path supports 4 channels)
-    
+
     * data processing modules ( DC filter, IQ Correction and Data format
       control)
     * ADC Channel register map

docs/library/axi_ad9643/index.rst

@@ -6,7 +6,7 @@ AXI AD9643 (OBSOLETE)
 .. warning::
 
    The support for :git-hdl:`AXI AD9643 <hdl_2016_r1:library/axi_ad9643>` IP
-   has been discontinued, the latest tested release being hdl_2016_r1.
+   has been discontinued, the latest tested release being ``hdl_2016_r1``.
    This page is for legacy purposes only.
 
 The :git-hdl:`AXI AD9643 <hdl_2016_r1:library/axi_ad9643>` IP core was used
@@ -158,7 +158,7 @@ delayed independently through the delay controller register map.
 For more information regarding the 7 Series primitives you can take a look at
 AMD Xilinx's user guides UG472, UG471 and UG953.
 
-The output of the interface module is fed to the channel modules. 
+The output of the interface module is fed to the channel modules.
 The channel module implements:
 
 * a PRBS monitor

docs/library/axi_ad9671/index.rst

@@ -5,11 +5,17 @@ AXI AD9671 (OBSOLETE)
 
 .. hdl-component-diagram::
 
-The :git-hdl:`AXI AD9671 <library/axi_ad9671>` IP core
+.. warning::
+
+   The support for :git-hdl:`AXI AD9671 <hdl_2022_r2:library/axi_ad9671>`
+   has been discontinued.
+   This page is kept for legacy purposes only.
+
+The :git-hdl:`AXI AD9671 <hdl_2022_r2:library/axi_ad9671>` IP core
 can be used to interface the :adi:`AD9671` Octal Ultrasound AFE with digital
 demodulator.
 An AXI Memory Map interface is used for configuration.
-Data is received from Xilinx JESD IP.
+Data is received from AMD Xilinx JESD IP.
 
 More about the generic framework interfacing ADCs can be read in :ref:`axi_adc`.
 

docs/library/axi_ad9963/index.rst

@@ -248,7 +248,7 @@ Software Support
 --------------------------------------------------------------------------------
 
 The software for this part can be found as part of the :adi:`ADALM2000`
-(or shortly, M2K) reference design. 
+(or shortly, M2K) reference design.
 
 * Linux device driver at :git-linux:`drivers/iio/adc/ad9963.c`
 

docs/library/axi_laser_driver/index.rst

@@ -71,17 +71,17 @@ Interface
        signal can be used for preconditioning various IPs of the data path.
    * - tia_chsel
      - Control lines for the TIA channel multiplexer.
-   * - irq 
+   * - irq
      - Interrupt signal.
 
 Register Map
 --------------------------------------------------------------------------------
 
 .. hdl-regmap::
-   :name: AXI_LASER_DRIVER 
+   :name: AXI_LASER_DRIVER
 
 References
 -------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/axi_laser_driver`
-* :dokuwiki:`AXI Laser Driver on wiki <resources/fpga/docs/axi_laser_driver>`
+* :dokuwiki:`AXI Laser Driver on wiki <resources/fpga/docs/axi_laser_driver>`

docs/library/axi_pwm_gen/index.rst

@@ -285,4 +285,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/axi_pwm_gen`
-* :dokuwiki:`AXI PWM GEN on wiki <resources/fpga/docs/axi_pwm_gen>`
+* :dokuwiki:`AXI PWM GEN on wiki <resources/fpga/docs/axi_pwm_gen>`

docs/library/axi_sysid/index.rst

@@ -251,4 +251,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/axi_sysid` and :git-hdl:`library/sysid_rom`
-* :dokuwiki:`System ID on wiki <resources/fpga/docs/axi_sysid>`
+* :dokuwiki:`System ID on wiki <resources/fpga/docs/axi_sysid>`

docs/library/common/ad_dds/index.rst

@@ -329,5 +329,5 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/common/ad_dds.v` and :git-hdl:`library/common/ad_dds_1.v`
-  and :git-hdl:`library/common/ad_dds_2.v` 
-* :dokuwiki:`Direct digital synthesis on wiki <resources/fpga/docs/dds>`
+  and :git-hdl:`library/common/ad_dds_2.v`
+* :dokuwiki:`Direct digital synthesis on wiki <resources/fpga/docs/dds>`

docs/library/corundum/index.rst

@@ -58,7 +58,7 @@ and it needs to be cloned alongside this repository.
    -  J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (`Thesis`_)
 
 .. _FCCM Paper: https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf
-.. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/ 
+.. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/
 .. _Thesis: https://escholarship.org/uc/item/3mc9070t
 
 References
@@ -67,4 +67,4 @@ References
 * HDL IP core at :git-hdl:`library/corundum`
 * HDL project at :git-hdl:`projects/ad_gmsl2eth_sl`
 * :ref:`ad_gmsl2eth_sl`
-* :adi:`AD-GMSL2ETH-SL`
+* :adi:`AD-GMSL2ETH-SL`

docs/library/data_offload/index.rst

@@ -494,4 +494,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/data_offload`
-* :dokuwiki:`Data Offload Engine on wiki <resources/fpga/docs/data_offload>`
+* :dokuwiki:`Data Offload Engine on wiki <resources/fpga/docs/data_offload>`

docs/library/index.rst

@@ -107,4 +107,4 @@ available sources can be found in the same archive.
    axi_ad9144/index
    axi_ad9371/index
    axi_ad9643/index
-   axi_ad9671/index
+   axi_ad9671/index

docs/library/spi_engine/index.rst

@@ -109,4 +109,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/spi_engine`
-* :dokuwiki:`SPI Engine on wiki <resources/fpga/peripherals/spi_engine>`
+* :dokuwiki:`SPI Engine on wiki <resources/fpga/peripherals/spi_engine>`

docs/library/spi_engine/instruction-format.rst

@@ -201,7 +201,7 @@ The CS Invert Mask Instructions allows the user to select on a per-pin basis
 whether the Chip Select will be active-low (default) or active-high (inverted).
 Note that the Chip-Select instructions should remain the same because the value
 of CS is inverted at the output register, and additional logic (e.g. reset
-counters) occurs when the CS active state is asserted. 
+counters) occurs when the CS active state is asserted.
 
 Since the physical values on the pins are inverted at the output, the current
 Invert Mask does not affect the use of the :ref:`spi_engine cs-instruction`. As
@@ -226,9 +226,9 @@ version 1.02.00 of the core.
      - reserved
      - Reserved for future use. Must always be set to 0.
    * - m
-     - Mask 
+     - Mask
      - Mask for selecting inverted CS channels. For the bits set to 1, the
-       corresponding channel will be inverted at the output. 
+       corresponding channel will be inverted at the output.
 
 .. _spi_engine configuration-registers:
 

docs/library/spi_engine/tutorial.rst

@@ -6,7 +6,7 @@ SPI Engine Tutorial - PulSAR-ADC
 The goal of this tutorial is to present the process of adding
 :ref:`spi_engine` support for an ADI precision converter or family of converters
 using a few simple steps.
-The target carrier is the Digilent Cora-z7s board using a PMOD connector.
+The target carrier is the Digilent Cora Z7S board using a PMOD connector.
 
 Evaluating the target device
 --------------------------------------------------------------------------------
@@ -18,7 +18,7 @@ They all share the same interface and the same PCB, the differences being found
 in their performance. The table below offers a comparison between the timing
 parameters of the SPI interface for these devices. Using this table we can see
 how much they have in common and where the key differences are. All the values
-are for 3.3V VIO since the Cora-z7s is only 3.3V capable.
+are for 3.3V VIO since the Cora Z7S is only 3.3V capable.
 
 +----------+----------+------+----------+----------+----------+----------+
 | Device   | Re       | KSPS | T\_      | T_CONV   | T_CYC    | T_ACQ    |
@@ -165,7 +165,7 @@ Key timing characteristics:
    750 ns T_CYC
    500 ns T_CONV
    250 ns T_ACQ
-   12 ns T_SCLK @ >3V VIO (cora pmod is 3V3)
+   12 ns T_SCLK @ >3V VIO (Cora PMOD is 3V3)
 
 Sample rate control
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/library/util_axis_fifo_asym/index.rst

@@ -178,4 +178,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/util_axis_fifo_asym`
-* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki <resources/fpga/docs/util_axis_fifo_asym>`
+* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki <resources/fpga/docs/util_axis_fifo_asym>`

docs/library/util_extract/index.rst

@@ -59,4 +59,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/util_extract/util_extract.v`
-* :dokuwiki:`UTIL EXTRACT on wiki <resources/fpga/docs/util_extract>`
+* :dokuwiki:`UTIL EXTRACT on wiki <resources/fpga/docs/util_extract>`

docs/library/util_pack/util_cpack2.rst

@@ -86,4 +86,4 @@ or 16 bits.
 References
 --------------------------------------------------------------------------------
 
-* HDL IP core at :git-hdl:`library/util_pack/util_cpack2`
+* HDL IP core at :git-hdl:`library/util_pack/util_cpack2`

docs/library/util_pack/util_upack2.rst

@@ -89,4 +89,4 @@ initiates a read from the DMA three out of four clock cycles.
 References
 --------------------------------------------------------------------------------
 
-* HDL IP core at :git-hdl:`library/util_pack/util_upack2`
+* HDL IP core at :git-hdl:`library/util_pack/util_upack2`

docs/library/util_rfifo/index.rst

@@ -102,4 +102,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/util_rfifo`
-* :dokuwiki:`UTIL RFIFO on wiki <resources/fpga/docs/util_rfifo>`
+* :dokuwiki:`UTIL RFIFO on wiki <resources/fpga/docs/util_rfifo>`

docs/library/util_var_fifo/index.rst

@@ -89,4 +89,4 @@ References
 --------------------------------------------------------------------------------
 
 * HDL IP core at :git-hdl:`library/util_var_fifo`
-* :dokuwiki:`UTIL VAR FIFO on wiki <resources/fpga/docs/util_var_fifo>`
+* :dokuwiki:`UTIL VAR FIFO on wiki <resources/fpga/docs/util_var_fifo>`

docs/library/util_wfifo/index.rst

@@ -85,4 +85,4 @@ Interface
 References
 --------------------------------------------------------------------------------
 
-* HDL IP core at :git-hdl:`library/util_wfifo`
+* HDL IP core at :git-hdl:`library/util_wfifo`

docs/library/xilinx/index.rst

@@ -8,5 +8,5 @@ Contents
 
 .. toctree::
    :maxdepth: 2
-   
+
    UTIL_ADXCVR <util_adxcvr/index>