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common: coraz7s: Add axi_iic_ard for evb eeprom #1517

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Dec 6, 2024
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common: coraz7s: Add axi_iic_ard for evb eeprom #1517

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c1b9224
common: coraz7s: Add IIC for Arduino SCL SDA
gastmaier Nov 1, 2024
2f87969
docs: Update addr/irq with common axi_iic_ard
gastmaier Nov 21, 2024
5702bd8
projects: Update addr/irq with coraz7s axi_iic_ard
gastmaier Nov 21, 2024
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13 changes: 6 additions & 7 deletions docs/projects/ad4170_asdz/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,6 @@ Instance Zynq*/DE10-Nano**
======================== =================
spi_ad4170_axi_regmap* 0x44A0_0000
axi_ad4170_dma* 0x44A3_0000
axi_ad4170_iic* 0x44A4_0000
spi_clkgen* 0x44A7_0000
axi_dmac_0** 0x0002_0000
axi_spi_engine_0** 0x0003_0000
Expand All @@ -92,10 +91,10 @@ I2C connections
- Address
- I2C subordinate
* - PL*
- axi_iic
- axi_ad4170_iic
- 0x44A4_0000
- ---
- iic_ard
- axi_iic_ard
- 0x4160_0000
- 24AA32A
* - PS**
- i2c1
- sys_hps_i2c1
Expand Down Expand Up @@ -184,8 +183,8 @@ Below are the Programmable Logic interrupts used in this project.
Instance name HDL Linux Zynq Actual Zynq
=================== === ========== ===========
axi_ad4170_dma 13 57 89
axi_ad4170_iic 12 56 88
spi_ad4170 11 55 87
spi_ad4170 12 56 88
axi_iic_ard 11 55 87
=================== === ========== ===========

================ === =============== ================
Expand Down
15 changes: 8 additions & 7 deletions docs/projects/ad57xx_ardz/index.rst
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Expand Up @@ -112,11 +112,11 @@ I2C connections
- Alias
- Address
- I2C subordinate
* - PS*
- iic_0
- iic_0_io
- ---
- ---
* - PL*
- iic_ard
- axi_ard_fmc
- 0x4160_0000
- 24AA32A
* - PS**
- i2c1
- sys_hps_i2c1
Expand Down Expand Up @@ -212,8 +212,9 @@ Below are the Programmable Logic interrupts used in this project.
=================== === ========== ===========
Instance name HDL Linux Zynq Actual Zynq
=================== === ========== ===========
ad57xx_tx_dma 12 56 88
spi_ad57xx 11 55 87
ad57xx_tx_dma 13 57 89
spi_ad57xx 12 56 88
axi_iic_ard 11 55 87
=================== === ========== ===========

================ === =============== ================
Expand Down
10 changes: 5 additions & 5 deletions docs/projects/cn0540/index.rst
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Expand Up @@ -79,9 +79,9 @@ added to the base address from HDL (see more at :ref:`architecture cpu-intercon-
======================== =================
Instance Zynq*/DE10-Nano**
======================== =================
axi_iic_ard* 0x4160_0000
spi_cn0540_axi_regmap* 0x44A0_0000
axi_cn0540_dma* 0x44A3_0000
axi_iic_cn0540* 0x44A4_0000
xadc_in* 0x44A5_0000
spi_clkgen* 0x44A7_0000
axi_dmac_0** 0x0002_0000
Expand Down Expand Up @@ -109,8 +109,8 @@ I2C connections
* - PL
- axi_iic
- axi_iic_cn0540
- 0x44A4_0000
- ---
- 0x4160_0000
- LTC2606
* - PS
- i2c1
- sys_hps_i2c1
Expand Down Expand Up @@ -249,8 +249,8 @@ Below are the Programmable Logic interrupts used in this project.
Instance name HDL Linux Zynq Actual Zynq
=================== === ========== ===========
axi_cn0540_dma 13 57 89
axi_iic_cn0540 12 56 88
spi_cn0540 11 55 87
spi_cn0540 12 56 88
axi_iic_ard 11 55 87
=================== === ========== ===========

================ === =============== ================
Expand Down
39 changes: 39 additions & 0 deletions docs/projects/cn0561/index.rst
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Expand Up @@ -118,6 +118,44 @@ odr_generator* 0x0004_0000

``*`` instantiated only for DE10-Nano

I2C connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. list-table:: ZedBoard
:widths: 20 20 20 20 20
:header-rows: 1

* - I2C type
- I2C manager instance
- Alias
- Address
- I2C subordinate
* - PL
- iic_fmc
- axi_iic_fmc
- 0x4162_0000
- M24C02
* - PL
- iic_main
- axi_iic_main
- 0x4160_0000
- ---

.. list-table:: CoraZ7S
:widths: 20 20 20 20 20
:header-rows: 1

* - I2C type
- I2C manager instance
- Alias
- Address
- I2C subordinate
* - PL
- iic_ard
- axi_ard_fmc
- 0x4160_0000
- M24C02

SPI connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Expand Down Expand Up @@ -188,6 +226,7 @@ Instance name HDL Linux Zynq Actual Zynq
=============== === ========== ===========
axi_cn0561_dma 13 57 89
spi_cn0561 12 56 88
axi_iic_ard 11 55 87
=============== === ========== ===========

Building the HDL project
Expand Down
4 changes: 2 additions & 2 deletions docs/projects/cn0579/index.rst
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Expand Up @@ -175,8 +175,8 @@ Below are the Programmable Logic interrupts used in this project.
============= === ========== =========== =============== ================
Instance name HDL Linux Zynq Actual Zynq Linux Cyclone V Actual Cyclone V
============= === ========== =========== =============== ================
cn0579_dma* 13 57 89 --- ---
axi_iic_dac* 12 56 88 --- ---
cn0579_dma* 12 56 88 --- ---
axi_iic_ard* 11 55 87 --- ---
cn0579_dma** 5 --- --- 45 77
============= === ========== =========== =============== ================

Expand Down
20 changes: 18 additions & 2 deletions docs/projects/pulsar_adc/index.rst
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Expand Up @@ -203,7 +203,7 @@ pulsar_adc_trigger_gen 0x44B0_0000
I2C connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. list-table::
.. list-table:: ZedBoard
:widths: 20 20 20 20 20
:header-rows: 1

Expand All @@ -223,9 +223,24 @@ I2C connections
- 0x4160_0000
- ---

.. list-table:: CoraZ7S
:widths: 20 20 20 20 20
:header-rows: 1

* - I2C type
- I2C manager instance
- Alias
- Address
- I2C subordinate
* - PL
- iic_ard
- axi_ard_fmc
- 0x4160_0000
- ---

.. note::

Only for AD40xx/ADAQ40xx
Only for AD40xx/ADAQ40xx

SPI connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand Down Expand Up @@ -291,6 +306,7 @@ Instance name HDL Linux Zynq Actual Zynq
================== === ========== ===========
axi_pulsar_adc_dma 13 57 89
spi_pulsar_adc 12 56 88
iic_fmc/ard 11 55 87
================== === ========== ===========

Building the HDL project
Expand Down
8 changes: 1 addition & 7 deletions projects/ad4170_asdz/common/ad4170_asdz_bd.tcl
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Expand Up @@ -4,7 +4,6 @@
###############################################################################

create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ad4170

create_bd_port -dir I adc_data_ready

Expand All @@ -22,9 +21,6 @@ set hier_spi_engine spi_ad4170

spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk

ad_ip_instance axi_iic axi_ad4170_iic
ad_connect iic_ad4170 axi_ad4170_iic/iic

# Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)

ad_ip_instance axi_clkgen spi_clkgen
Expand Down Expand Up @@ -76,14 +72,12 @@ ad_connect sys_cpu_resetn axi_ad4170_dma/m_dest_axi_aresetn

ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad_cpu_interconnect 0x44a30000 axi_ad4170_dma
ad_cpu_interconnect 0x44a40000 axi_ad4170_iic
ad_cpu_interconnect 0x44a70000 spi_clkgen

# interrupts

ad_cpu_interrupt "ps-13" "mb-13" axi_ad4170_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" axi_ad4170_iic/iic2intc_irpt
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq

# memory interconnects

Expand Down
3 changes: 0 additions & 3 deletions projects/ad4170_asdz/coraz7s/system_constr.xdc
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Expand Up @@ -15,9 +15,6 @@ set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33}
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[1]] ; ## CK_IO7
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[0]] ; ## CK_IO2

set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_scl] ; ## CK_SCL
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_sda] ; ## CK_SDA

# rename auto-generated clock for SPI Engine to spi_clk - 40MHz
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]

Expand Down
10 changes: 5 additions & 5 deletions projects/ad4170_asdz/coraz7s/system_top.v
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Expand Up @@ -63,8 +63,8 @@ module system_top (
inout [1:0] btn,
inout [5:0] led,

inout iic_eeprom_scl,
inout iic_eeprom_sda,
inout iic_ard_scl,
inout iic_ard_sda,

// ad4170
input ad4170_spi_miso,
Expand Down Expand Up @@ -141,8 +141,6 @@ module system_top (
.adc_spi_cs (ad4170_spi_csn),
.adc_spi_sclk (ad4170_spi_sclk),
.adc_data_ready (ad4170_dig_aux[0]),
.iic_ad4170_scl_io (iic_eeprom_scl),
.iic_ad4170_sda_io (iic_eeprom_sda),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
Expand All @@ -160,6 +158,8 @@ module system_top (
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o());
.spi1_sdo_o (),
.iic_ard_scl_io (iic_ard_scl),
.iic_ard_sda_io (iic_ard_sda));

endmodule
4 changes: 2 additions & 2 deletions projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
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Expand Up @@ -71,8 +71,8 @@ ad_cpu_interconnect 0x44b10000 axi_ad57xx_clkgen

# interrupts

ad_cpu_interrupt "ps-12" "mb-12" ad57xx_dma/irq
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
ad_cpu_interrupt "ps-13" "mb-13" ad57xx_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq

# memory interconnects

Expand Down
8 changes: 0 additions & 8 deletions projects/ad57xx_ardz/coraz7s/system_bd.tcl
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Expand Up @@ -13,12 +13,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9

sysid_gen_sys_init_file

#the eval board requires an extra i2c channel for the coraz7s project
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io

ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO

ad_connect iic_0_io sys_ps7/IIC_0

source ../common/ad57xx_ardz_bd.tcl
3 changes: 0 additions & 3 deletions projects/ad57xx_ardz/coraz7s/system_constr.xdc
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Expand Up @@ -5,9 +5,6 @@

# ad57xx interface

set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_scl]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_sda]

set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_mosi]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_miso]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_sclk]
Expand Down
9 changes: 5 additions & 4 deletions projects/ad57xx_ardz/coraz7s/system_top.v
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Expand Up @@ -63,9 +63,10 @@ module system_top (
inout [1:0] btn,
inout [5:0] led,

inout iic_ard_scl,
inout iic_ard_sda,

// ad57xx ardz
inout ad57xx_ardz_scl,
inout ad57xx_ardz_sda,
input ad57xx_ardz_spi_miso,
output ad57xx_ardz_spi_mosi,
output ad57xx_ardz_spi_sclk,
Expand Down Expand Up @@ -137,8 +138,6 @@ module system_top (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.iic_0_io_scl_io (ad57xx_ardz_scl),
.iic_0_io_sda_io (ad57xx_ardz_sda),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
Expand All @@ -157,6 +156,8 @@ module system_top (
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.iic_ard_scl_io (iic_ard_scl),
.iic_ard_sda_io (iic_ard_sda),
.ad57xx_spi_sdo (ad57xx_ardz_spi_mosi),
.ad57xx_spi_sdo_t (),
.ad57xx_spi_sdi (ad57xx_ardz_spi_miso),
Expand Down
6 changes: 6 additions & 0 deletions projects/ad719x_asdz/coraz7s/system_top_pmod.v
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Expand Up @@ -63,6 +63,9 @@ module system_top (
inout [ 1:0] btn,
inout [ 5:0] led,

inout iic_ard_scl,
inout iic_ard_sda,

// ad7190 spi pins

output adc_spi_sclk,
Expand Down Expand Up @@ -142,6 +145,9 @@ module system_top (
.spi0_sdo_i (1'b0),
.spi0_sdo_o (adc_spi_mosi),

.iic_ard_scl_io (iic_ard_scl),
.iic_ard_sda_io (iic_ard_sda),

.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
Expand Down
8 changes: 1 addition & 7 deletions projects/cn0540/common/cn0540_bd.tcl
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Expand Up @@ -4,7 +4,6 @@
###############################################################################

create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_mux
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux9
Expand All @@ -29,9 +28,6 @@ set hier_spi_engine spi_cn0540

spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk

ad_ip_instance axi_iic axi_iic_cn0540
ad_connect iic_cn0540 axi_iic_cn0540/iic

# Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)

ad_ip_instance axi_clkgen spi_clkgen
Expand Down Expand Up @@ -100,15 +96,13 @@ ad_connect xadc_in/Vaux15 xadc_vaux15

ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
ad_cpu_interconnect 0x44a50000 xadc_in
ad_cpu_interconnect 0x44a70000 spi_clkgen

# interrupts

ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq
ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq

# memory interconnects

Expand Down
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