i3c_controller: Bug fixes for I2C devices and lower sclk speed #1514
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gastmaier
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IuliaCMoldovan,
StancaPop,
LBFFilho and
sarpadi
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gastmaier
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There is no guarantee that the device driver will use the same xfer (to yield repeated start (Sr)), for multiple concurrent transfer. Instead, it may queue multiple xfers which generate (...Stop)+(Start...). This case would cause the bit modulation to yield a [Stop+RepeatedStart], generating an "extra" clock bit. Check for the bit-mod if the current state is Stop, if so, clear the autoset Sr state reg, ensuring a [Stop+Start]. Signed-off-by: Jorge Marques <[email protected]>
I2C RX transfers should stop with last ACK-bit as a NACK and then a stop, previously, the controller would ACK all bytes and then stop. Signed-off-by: Jorge Marques <[email protected]>
For backwards compatibility with slow I2C devices (100kHz, 400kHz), add a parameter to further divide the open drain speed. I3C devices still operate at 1.5MHz in open drain mode, since the I3C clock cycles are filtered by the I2C 50ns Spike filter. Signed-off-by: Jorge Marques <[email protected]>
Signed-off-by: Jorge Marques <[email protected]>
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PR Description
Some rework to better support slow I2C devices (100kHz, 400kHz).
I2C speed can be lower than I3C open drain speed.
The new I2C_MOD allows to configure this speed.
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