Fixes for AD9164 on ZCU102 #1511
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PopPaul2021
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IuliaCMoldovan,
AndrDragomir and
bluncan
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Documentation update PR: #1510 |
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acostina
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Nov 29, 2024
Changes made: - adding MODE 09 for AD9614 device - changing the source DMA DATA WIDTH to 128 - changing the TX_LANE_INVERT from 0x0F to 0xF0 - updating the xcvr parameters for 12.5GHz lane rate - cosmetics on the system_constr file Signed-off-by: PopPaul2021 <[email protected]>
If the parameters are not listed in any of the supported modes, the user can configure them through make parameters. e.g.: make ADI_DAC_DEVICE=AD9164 M=1 L=8 S=4 F=1 HD=1 N=16 NP=16 or make ADI_DAC_DEVICE=AD9164 ADI_DAC_MODE=08 M=1 S=4 This will result in the same configuration: M=1 L=8 S=4 F=1 HD=1 N=16 NP=16 Signed-off-by: PopPaul2021 <[email protected]>
The ADI_LANE_RATE parameter is added on ZCU102 project. The parameter can take the 12.5GHz OR 15.4GHz values. The default value is 15.4GHz. Signed-off-by: PopPaul2021 <[email protected]>
The 240 LANE_INVERT value is specific only for the AD9161, AD9162, AD9163 and AD9164. Signed-off-by: PopPaul2021 <[email protected]>
Signed-off-by: PopPaul2021 <[email protected]>
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IuliaCMoldovan
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