Add AD4052-ARDZ project

[gastmaier]

PR Description

Adds support to the AD4052 ADC SPI family (AD4050, AD4052, AD4056, AD4058).
The CNV pin contains a OR logic for:

• In buffer reading mode, conversions are triggered by the pwm generator.
• In single shot mode, conversions are triggered by a GPIO.

SPI Engine Offload waits the Data Ready signal from the ADC, configured at pin GP1.
ADC GP0 is used as a monitor pin, triggering either threshold (rising+failing) events to the PS.

Named ad4052 instead of ad405x since the ad4052 is the main part of the family (best granularity and speed).

Pointers:
www.analog.com/ad4050
www.analog.com/ad4052
www.analog.com/eval-ad4052-ardz.html

Coraz7s tested on HW. Pending De10Nano

The de10nano raises the same critical warnings as #1463

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[gastmaier]

Applied review changes.
Increased compilation effort to close timing at spi_clk 150Mhz

[sarpadi]

why is this level of CNV control not available on the de10nano approach ?

[gastmaier]

My oversight.

[gastmaier]

Merge after #1517