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AD7616: Add AXI ADC support #1477

Merged
merged 3 commits into from
Dec 9, 2024
Merged

AD7616: Add AXI ADC support #1477

merged 3 commits into from
Dec 9, 2024

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PIoandan
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@PIoandan PIoandan commented Oct 1, 2024

PR Description

Add AXI ADC support to existing AD7616 PIF project.
Update AD7616 project to account for the changes (add CPACK core, fix DMA connections).
Update AXI_AD7616 and AD7616 (project) documentation and block diagrams

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@@ -67,7 +82,7 @@ module axi_ad7616_pif #(
input rd_req,
input wr_req,
input [15:0] wr_data,
output reg [15:0] rd_data,
output reg [15:0] rd_data = 'ha1b2,
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Remove / fix initialization

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Done.

@@ -96,10 +111,20 @@ module axi_ad7616_pif #(

reg rd_valid_d = 1'h0;

reg [ 4:0] channel_counter = 5'h0;
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fix spacing, separate reg from wire reclarations, initializations

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Done.

rd_req_edge_d <= rd_req_edge;
end

//channel_counter
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irrelevant comment. delete or elaborate

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Removed.


wire [255:0] adc_data_s;

wire [ 7:0] adc_custom_control;
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spacing cleanup

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Done.

end
endgenerate

axi_ad7616_pif #(
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fix indentation

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Done.

assign adc_data_1 = dma_data[14*16+15:14*16];
assign adc_data_0 = dma_data[15*16+15:15*16];

wire [31:0] adc_config_ctrl;
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move declaration

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Done.

@sarpadi
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sarpadi commented Nov 27, 2024

Update system_project.tcl with newer build parameter handling

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sarpadi commented Nov 27, 2024

fix conflicts

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remove 100MHz clock gen core and use PS clk (sys_clk) instead

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Done.

@PIoandan PIoandan force-pushed the dev_axi_ad7616 branch 3 times, most recently from 5711fcc to 14394f4 Compare November 28, 2024 12:18
@PIoandan PIoandan marked this pull request as ready for review November 28, 2024 12:20
@PIoandan PIoandan requested a review from sarpadi November 28, 2024 12:20
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Made a squash for all three categories of files.

docs/library/axi_ad7616/index.rst Outdated Show resolved Hide resolved
docs/library/axi_ad7616/index.rst Show resolved Hide resolved
docs/library/axi_ad7616/index.rst Show resolved Hide resolved
projects/ad7616_sdz/zed/Makefile Show resolved Hide resolved
docs/projects/ad7616_sdz/index.rst Outdated Show resolved Hide resolved
library/axi_ad7616/axi_ad7616.v Outdated Show resolved Hide resolved
library/axi_ad7616/axi_ad7616_ip.tcl Outdated Show resolved Hide resolved
Signed-off-by: Pop Ioan Daniel <[email protected]>
Signed-off-by: Pop Ioan Daniel <[email protected]>
@PIoandan PIoandan merged commit 71f59dc into main Dec 9, 2024
2 of 5 checks passed
@PIoandan PIoandan deleted the dev_axi_ad7616 branch December 9, 2024 14:21
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3 participants