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ad4858_fmcz #1098

Merged
merged 2 commits into from
Oct 5, 2023
Merged

ad4858_fmcz #1098

merged 2 commits into from
Oct 5, 2023

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AndreiGrozav
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Initial design.
Tested in hardware.

@AndreiGrozav AndreiGrozav requested a review from a team March 15, 2023 15:10
IuliaCMoldovan
IuliaCMoldovan previously approved these changes Aug 11, 2023
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Looks good to me now

IuliaCMoldovan
IuliaCMoldovan previously approved these changes Aug 11, 2023
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IuliaCMoldovan
IuliaCMoldovan previously approved these changes Aug 18, 2023
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IuliaCMoldovan
IuliaCMoldovan previously approved these changes Sep 20, 2023
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IuliaCMoldovan
IuliaCMoldovan previously approved these changes Sep 28, 2023
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IuliaCMoldovan
IuliaCMoldovan previously approved these changes Sep 29, 2023
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PopPaul2021
PopPaul2021 reviewed Oct 2, 2023
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library/axi_ad4858/axi_ad4858_ip.tcl Outdated

set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc]

# UNCOMENT when entering hdl repo
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Shouldn't this comment be removed?

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Yes

projects/ad4858_fmcz/Readme.md Outdated
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Can you please also add the make parameters that could be used?

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Done

@PopPaul2021 PopPaul2021 self-requested a review October 2, 2023 08:33
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PopPaul2021 previously approved these changes Oct 2, 2023
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Looks good to me! Both CMOS and LVDS modes were built without errors or critical warnings.

IuliaCMoldovan
IuliaCMoldovan previously approved these changes Oct 2, 2023
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alin724
alin724 previously approved these changes Oct 2, 2023
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Looks good. The library/Makefile file would need an update to latest master-based version.

@AndreiGrozav AndreiGrozav dismissed stale reviews from alin724 and IuliaCMoldovan via 6ade8da October 3, 2023 07:26
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I squashed the latest commits from requests and fixed the conflict in the library/Makefile. The Makefile had an addition of another IP in the main branch.

@AndreiGrozav
axi_ad4858: Initial commit
6e042a2 
The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC.
Features:
 - AXI based configuration
 - LVDS and CMOS support
 - Configurable number of active data lines (CMOS - build-time configurable)
 - Oversampling support
 - Supports packet formats 0,1,2 or 3
 - CRC check support
 - Real-time data header access
 - Channel based raw data access(0x0408)
 - Xilinx devices compatible

Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
@AndreiGrozav
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V2:

  1. Update commit messages.
  2. Remove wiki link integration in up_adc_common table.

@alin724 alin724 self-requested a review October 3, 2023 12:14
@AndreiGrozav
ad4858_fmcz: Initial design
9e7c20b 
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.

The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)

Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
@PopPaul2021 PopPaul2021 self-requested a review October 5, 2023 06:00
@AndreiGrozav AndreiGrozav merged commit cde9956 into master Oct 5, 2023
1 of 2 checks passed
@AndreiGrozav AndreiGrozav deleted the dev_ad4858_fmcz branch October 5, 2023 07:19
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@PopPaul2021 PopPaul2021 PopPaul2021 approved these changes

@alin724 alin724 alin724 approved these changes

@IuliaCMoldovan IuliaCMoldovan IuliaCMoldovan approved these changes

@acostina acostina acostina approved these changes

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@AndreiGrozav @acostina @IuliaCMoldovan @alin724 @PopPaul2021