library:axi_ad7616: Fix timing specifications

Fix delay specification between CS and RD signals.

Signed-off-by: Pop Ioan Daniel <[email protected]>

library/axi_ad7616/axi_ad7616_pif.v

@@ -307,7 +307,7 @@ module axi_ad7616_pif #(
   end
 
   assign adc_valid = adc_valid_s;
-  assign cs_n = (transfer_state == IDLE) || (rd_n == 1'b1) ? 1'b1 : 1'b0;
+  assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
   assign db_t = ~wr_req_edge_d;
   assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_edge_d == 1'b1)) ||
                   (transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;