ace: coraz7s: Add project

Common coraz7s project with added IIC Controller on Arduino SCL/SDA pins to *try* to read the EEPROM of compatible boards. Software is responsible to catch I2C driver probe failing and act accordingly. Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Nov 11, 2024 · dc93756 · dc93756
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diff --git a/projects/ace/Makefile b/projects/ace/Makefile
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+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
diff --git a/projects/ace/Readme.md b/projects/ace/Readme.md
@@ -0,0 +1,18 @@
+# AD4052-ARDZ HDL Project
+
+Here are some pointers to help you:
+  * [Board Product Page](https://www.analog.com/eval-ad400x-fmcz)
+  * Parts : [AD4050:  Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4050)
+  * Parts : [AD4052:  Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4052)
+  * Parts : [AD4056:  Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4056)
+  * Parts : [AD4058:  Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4058)
+
+  * HDL Doc: https://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html
+  * Linux Drivers: https://github.com/analogdevicesinc/linux/tree/staging/ad4052/drivers/iio/adc/ad4052.c
+
+## Supported parts
+
+  * AD4050
+  * AD4052
+  * AD4056
+  * AD4058
diff --git a/projects/ace/common/ace_bd.tcl b/projects/ace/common/ace_bd.tcl
@@ -0,0 +1,14 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_eeprom
+
+ad_ip_instance axi_iic axi_iic_eeprom
+
+ad_connect iic_eeprom axi_iic_eeprom/iic
+
+ad_cpu_interconnect 0x44a40000 axi_iic_eeprom
+
+ad_cpu_interrupt "ps-11" "mb-11" axi_iic_eeprom/iic2intc_irpt
diff --git a/projects/ace/common/evb_arduino_iic.txt b/projects/ace/common/evb_arduino_iic.txt
@@ -0,0 +1,6 @@
+Header/Pin            Schematic_name     Device.Pin         System_top_name        IOSTANDARD  Termination
+
+# evb_arduino_iic
+
+P3.10                 SCL_ARD            EEPROM.SCL         iic_eeprom_scl         LVCMOS33    #N/A
+P3.9                  SDA_ARD            EEPROM.SDA         iic_eeprom_sda         LVCMOS33    #N/A
diff --git a/projects/ace/coraz7s/Makefile b/projects/ace/coraz7s/Makefile
@@ -0,0 +1,19 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ace_coraz7s
+
+M_DEPS += ../common/ace_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ace/coraz7s/system_bd.tcl b/projects/ace/coraz7s/system_bd.tcl
@@ -0,0 +1,15 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source ../common/ace_bd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
diff --git a/projects/ace/coraz7s/system_constr.xdc b/projects/ace/coraz7s/system_constr.xdc
@@ -0,0 +1,8 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# EEPROM IIC interface
+set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33}          [get_ports iic_eeprom_scl] ; ## Arduino_SCL
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33}          [get_ports iic_eeprom_sda] ; ## Arduino_SDA
diff --git a/projects/ace/coraz7s/system_project.tcl b/projects/ace/coraz7s/system_project.tcl
@@ -0,0 +1,18 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ace_coraz7s
+
+adi_project_files ace_coraz7s [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top.v" \
+    "system_constr.xdc" \
+    "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+adi_project_run ace_coraz7s
diff --git a/projects/ace/coraz7s/system_top.v b/projects/ace/coraz7s/system_top.v
@@ -0,0 +1,145 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout   [ 1:0]  btn,
+  inout   [ 5:0]  led,
+
+  inout           iic_eeprom_scl,
+  inout           iic_eeprom_sda
+);
+
+  // internal signals
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+ // assignments
+  assign gpio_i[63:32] = gpio_o[63:32];
+  assign gpio_i[31:8] = gpio_o[31:8];
+
+  // instantiations
+  ad_iobuf #(
+    .DATA_WIDTH (2)
+  ) i_iobuf_buttons (
+    .dio_t (gpio_t[1:0]),
+    .dio_i (gpio_o[1:0]),
+    .dio_o (gpio_i[1:0]),
+    .dio_p (btn));
+
+  ad_iobuf #(
+    .DATA_WIDTH (6)
+  ) i_iobuf_leds (
+    .dio_t (gpio_t[7:2]),
+    .dio_i (gpio_o[7:2]),
+    .dio_o (gpio_i[7:2]),
+    .dio_p (led));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (1'b0),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .iic_eeprom_scl_io(iic_eeprom_scl),
+    .iic_eeprom_sda_io(iic_eeprom_sda));
+
+endmodule