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library/axi_ad3552r: Added DDS option as input source.
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Signed-off-by: PopPaul2021 <[email protected]>
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@PopPaul2021
PopPaul2021 committed Jun 26, 2023
1 parent c1f40af commit b2574a0
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Showing 5 changed files with 90 additions and 17 deletions.
7 changes: 7 additions & 0 deletions library/axi_ad3552r/Makefile
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Expand Up @@ -6,6 +6,13 @@

LIBRARY_NAME := axi_ad3552r

GENERIC_DEPS += ../common/ad_addsub.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_2.v
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
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12 changes: 10 additions & 2 deletions library/axi_ad3552r/axi_ad3552r.v
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Expand Up @@ -41,7 +41,11 @@ module axi_ad3552r #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0
parameter DEV_PACKAGE = 0,
parameter DDS_DISABLE = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
) (

// DAC INTERFACE
Expand Down Expand Up @@ -159,7 +163,11 @@ module axi_ad3552r #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.FPGA_FAMILY(FPGA_FAMILY),
.SPEED_GRADE(SPEED_GRADE),
.DEV_PACKAGE(DEV_PACKAGE)
.DEV_PACKAGE(DEV_PACKAGE),
.DDS_DISABLE(DDS_DISABLE),
.DDS_TYPE(DDS_TYPE),
.DDS_CORDIC_DW(DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW)
) axi_ad3552r_up_core (
.dac_clk(dac_clk),
.dac_rst(dac_rst_s),
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61 changes: 50 additions & 11 deletions library/axi_ad3552r/axi_ad3552r_channel.v
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Expand Up @@ -37,7 +37,11 @@

module axi_ad3552r_channel #(

parameter CHANNEL_ID = 32'h0
parameter CHANNEL_ID = 32'h0,
parameter DDS_DISABLE = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
) (

// dac interface
Expand Down Expand Up @@ -81,6 +85,15 @@ module axi_ad3552r_channel #(
wire [ 3:0] dac_data_sel_s;
wire dac_data_valid_int;
wire [15:0] dac_data_int;
wire [15:0] dac_dds_data_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;

reg [15:0] ramp_pattern = 16'h0000;
reg ramp_valid = 1'b0;
Expand All @@ -94,9 +107,14 @@ module axi_ad3552r_channel #(
assign formatted_adc_data [14:0] = adc_data[14:0];

assign dac_data_int = (dac_data_sel_s == 4'hb) ? ramp_pattern :
((dac_data_sel_s == 4'h3) ? 16'b0 : ((dac_data_sel_s == 4'h8) ? formatted_adc_data : formatted_dma_data));
((dac_data_sel_s == 4'h3) ? 16'b0 :
(((dac_data_sel_s == 4'h8) ? formatted_adc_data :
((dac_data_sel_s == 4'h2) ? formatted_dma_data: dac_dds_data_s ))));

assign dac_data_valid_int = (dac_data_sel_s == 4'hb) ? ramp_valid :
((dac_data_sel_s == 4'h3) ? 1'b1 : ((dac_data_sel_s == 4'h8) ? valid_in_adc : valid_in_dma));
((dac_data_sel_s == 4'h3) ? 1'b1 :
(((dac_data_sel_s == 4'h8) ? valid_in_adc :
((dac_data_sel_s == 4'h2) ? valid_in_dma: 1'b1 ))));

// ramp generator

Expand All @@ -112,21 +130,42 @@ module axi_ad3552r_channel #(
end
end

ad_dds #(
.DISABLE (DDS_DISABLE),
.DDS_DW (16),
.PHASE_DW (16),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.CLK_RATIO (1)
) i_dds (
.clk (dac_clk),
.dac_dds_format (dac_dfmt_type),
.dac_data_sync (dac_data_sync),
.dac_valid (dac_data_ready),
.tone_1_scale (dac_dds_scale_1_s),
.tone_2_scale (dac_dds_scale_2_s),
.tone_1_init_offset (dac_dds_init_1_s),
.tone_2_init_offset (dac_dds_init_2_s),
.tone_1_freq_word (dac_dds_incr_1_s),
.tone_2_freq_word (dac_dds_incr_2_s),
.dac_dds_data (dac_dds_data_s));

// single channel processor

up_dac_channel #(
.CHANNEL_ID(CHANNEL_ID)
) dac_channel (
.dac_clk(dac_clk),
.dac_rst(dac_rst),
.dac_dds_scale_1(),
.dac_dds_init_1(),
.dac_dds_incr_1(),
.dac_dds_scale_2(),
.dac_dds_init_2(),
.dac_dds_incr_2(),
.dac_pat_data_1(),
.dac_pat_data_2(),
.dac_dds_scale_1(dac_dds_scale_1_s),
.dac_dds_init_1(dac_dds_init_1_s),
.dac_dds_incr_1(dac_dds_incr_1_s),
.dac_dds_scale_2(dac_dds_scale_2_s),
.dac_dds_init_2(dac_dds_init_2_s),
.dac_dds_incr_2(dac_dds_incr_2_s),
.dac_pat_data_1(dac_pat_data_1_s),
.dac_pat_data_2(dac_pat_data_2_s),
.dac_data_sel(dac_data_sel_s),
.dac_mask_enable(),
.dac_iq_mode(),
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20 changes: 16 additions & 4 deletions library/axi_ad3552r/axi_ad3552r_core.v
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Expand Up @@ -40,7 +40,11 @@ module axi_ad3552r_core #(
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0
parameter DEV_PACKAGE = 0,
parameter DDS_DISABLE = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
) (

// dac interface
Expand Down Expand Up @@ -133,7 +137,11 @@ module axi_ad3552r_core #(
// DAC CHANNEL 0

axi_ad3552r_channel #(
.CHANNEL_ID(0)
.CHANNEL_ID(0),
.DDS_DISABLE(DDS_DISABLE),
.DDS_TYPE(DDS_TYPE),
.DDS_CORDIC_DW(DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW)
) axi_ad3552r_channel_0 (
.dac_clk(dac_clk),
.dac_rst(dac_rst_s),
Expand All @@ -160,7 +168,11 @@ module axi_ad3552r_core #(
// DAC CHANNEL 1

axi_ad3552r_channel #(
.CHANNEL_ID(1)
.CHANNEL_ID(1),
.DDS_DISABLE(DDS_DISABLE),
.DDS_TYPE(DDS_TYPE),
.DDS_CORDIC_DW(DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW)
) axi_ad3552r_channel_1(
.dac_clk(dac_clk),
.dac_rst(dac_rst_s),
Expand Down Expand Up @@ -218,7 +230,7 @@ module axi_ad3552r_core #(
.dac_status(),
.dac_sync_in_status(),
.dac_status_unf(),
.dac_clk_ratio(32'd2),
.dac_clk_ratio(32'd1),
.up_dac_ce(),
.up_pps_rcounter(32'd0),
.up_pps_status(1'd0),
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7 changes: 7 additions & 0 deletions library/axi_ad3552r/axi_ad3552r_ip.tcl
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Expand Up @@ -11,6 +11,13 @@ adi_ip_files axi_ad3552r [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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