ad4052_ardz: coraz7s: Add project

Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Dec 3, 2024 · 7fd11f6 · 7fd11f6
1 parent 5702bd8
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diff --git a/projects/ad4052_ardz/Makefile b/projects/ad4052_ardz/Makefile
@@ -0,0 +1,7 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
diff --git a/projects/ad4052_ardz/Readme.md b/projects/ad4052_ardz/Readme.md
@@ -0,0 +1,19 @@
+# AD4052-ARDZ HDL Project
+
+Here are some pointers to help you:
+  * [Board Product Page](https://www.analog.com/eval-ad4050-ardz)
+  * [Board Product Page](https://www.analog.com/eval-ad4052-ardz)
+  * Parts : [AD4050:  Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4050)
+  * Parts : [AD4052:  Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4052)
+  * Parts : [AD4056:  Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4056)
+  * Parts : [AD4058:  Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4058)
+
+  * HDL Doc: https://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html
+  * Linux Drivers: https://github.com/analogdevicesinc/linux/tree/staging/ad4052/drivers/iio/adc/ad4052.c
+
+## Supported parts
+
+  * AD4050
+  * AD4052
+  * AD4056
+  * AD4058
diff --git a/projects/ad4052_ardz/common/ad4052_bd.tcl b/projects/ad4052_ardz/common/ad4052_bd.tcl
@@ -0,0 +1,74 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_port -dir O adc_cnv
+create_bd_port -dir I adc_gp1_n
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
+
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set data_width    32
+set async_spi_clk 1
+set num_cs        1
+set num_sdi       1
+set num_sdo       1
+set sdi_delay     1
+set echo_sclk     0
+
+set hier_spi_engine spi_adc
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+
+ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
+
+ad_ip_instance axi_clkgen spi_clkgen
+ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 4
+ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
+ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6
+
+ad_ip_instance axi_pwm_gen adc_trigger_gen
+ad_ip_parameter adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
+ad_ip_parameter adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
+
+# dma to receive data stream
+ad_ip_instance axi_dmac axi_adc_dma
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_SRC 1
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_DEST 0
+ad_ip_parameter axi_adc_dma CONFIG.CYCLIC 0
+ad_ip_parameter axi_adc_dma CONFIG.SYNC_TRANSFER_START 0
+ad_ip_parameter axi_adc_dma CONFIG.AXI_SLICE_SRC 0
+ad_ip_parameter axi_adc_dma CONFIG.AXI_SLICE_DEST 1
+ad_ip_parameter axi_adc_dma CONFIG.DMA_2D_TRANSFER 0
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+
+ad_connect $sys_cpu_clk spi_clkgen/clk
+ad_connect spi_clk spi_clkgen/clk_0
+
+ad_connect spi_clk adc_trigger_gen/ext_clk
+ad_connect $sys_cpu_clk adc_trigger_gen/s_axi_aclk
+ad_connect sys_cpu_resetn adc_trigger_gen/s_axi_aresetn
+ad_connect $hier_spi_engine/trigger adc_gp1_n
+ad_connect adc_trigger_gen/pwm_0 adc_cnv
+
+ad_connect axi_adc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+ad_connect $hier_spi_engine/m_spi adc_spi
+
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect spi_clk $hier_spi_engine/spi_clk
+ad_connect spi_clk axi_adc_dma/s_axis_aclk
+ad_connect sys_cpu_resetn $hier_spi_engine/resetn
+ad_connect sys_cpu_resetn axi_adc_dma/m_dest_axi_aresetn
+
+ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
+ad_cpu_interconnect 0x44a30000 axi_adc_dma
+ad_cpu_interconnect 0x44a70000 spi_clkgen
+ad_cpu_interconnect 0x44b00000 adc_trigger_gen
+
+ad_cpu_interrupt "ps-13" "mb-13" axi_adc_dma/irq
+ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq
+
+ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect $sys_cpu_clk axi_adc_dma/m_dest_axi
diff --git a/projects/ad4052_ardz/common/eval_ad4052_ardz.txt b/projects/ad4052_ardz/common/eval_ad4052_ardz.txt
@@ -0,0 +1,13 @@
+Header/Pin            Schematic_name     Device.Pin         System_top_name        IOSTANDARD  Termination
+
+# eval_ad4052_ardz
+
+P3.10                 SCL_ARD            EEPROM.SCL         iic_eeprom_scl         LVCMOS33    #N/A
+P3.9                  SDA_ARD            EEPROM.SDA         iic_eeprom_sda         LVCMOS33    #N/A
+P3.6                  SCLK_ARD           AD4052.SCLK        adc_spi_sclk           LVCMOS33    IOB TRUE
+P3.5                  MISO_ARD           AD4052.SDO         adc_spi_sdi            LVCMOS33    IOB TRUE
+P3.4                  MOSI_ARD           AD4052.SDI         adc_spi_sdo            LVCMOS33    IOB TRUE
+P3.3                  CSB_ARD            AD4052.CSB         adc_spi_cs             LVCMOS33    IOB TRUE
+P4.7                  CNV_ARD            AD4052.CNV         adc_spi_cnv            LVCMOS33    IOB TRUE
+P3.2                  D9_ARD             AD4052.GP0         adc_spi_gpio0          LVCMOS33    #N/A
+P3.1                  D8_ARD             AD4052.GP1         adc_spi_gpio1          LVCMOS33    #N/A
diff --git a/projects/ad4052_ardz/coraz7s/Makefile b/projects/ad4052_ardz/coraz7s/Makefile
@@ -0,0 +1,27 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad4052_ardz_coraz7s
+
+M_DEPS += ../common/ad4052_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_sysid
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ad4052_ardz/coraz7s/system_bd.tcl b/projects/ad4052_ardz/coraz7s/system_bd.tcl
@@ -0,0 +1,15 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source ../common/ad4052_bd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
diff --git a/projects/ad4052_ardz/coraz7s/system_constr.xdc b/projects/ad4052_ardz/coraz7s/system_constr.xdc
@@ -0,0 +1,23 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ADC SPI interface
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sclk]   ; ## Arduino_IO13
+set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sdi]    ; ## Arduino_IO12
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sdo]    ; ## Arduino_IO11
+set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_cs]     ; ## Arduino_IO10
+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33}          [get_ports adc_cnv]        ; ## Arduino_IO06
+set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33}          [get_ports adc_gp0]        ; ## Arduino_IO09
+set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33}          [get_ports adc_gp1]        ; ## Arduino_IO08
+
+# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
+# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
+create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
+
+# relax the SDO path to help closing timing at high frequencies
+set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
+set_multicycle_path -hold  7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
+set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
+set_multicycle_path -hold  7 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
diff --git a/projects/ad4052_ardz/coraz7s/system_project.tcl b/projects/ad4052_ardz/coraz7s/system_project.tcl
@@ -0,0 +1,18 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad4052_ardz_coraz7s
+
+adi_project_files ad4052_ardz_coraz7s [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+    "system_top.v" \
+    "system_constr.xdc" \
+    "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+adi_project_run ad4052_ardz_coraz7s
diff --git a/projects/ad4052_ardz/coraz7s/system_top.v b/projects/ad4052_ardz/coraz7s/system_top.v
@@ -0,0 +1,173 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout   [ 1:0]  btn,
+  inout   [ 5:0]  led,
+
+  inout           iic_ard_scl,
+  inout           iic_ard_sda,
+
+  output          adc_spi_sclk,
+  input           adc_spi_sdi,
+  output          adc_spi_sdo,
+  output          adc_spi_cs,
+  output          adc_cnv,
+  inout           adc_gp1,
+  inout           adc_gp0
+);
+
+  // internal signals
+
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+  wire            adc_cnv_w;
+  wire            adc_gp1_n = ~adc_gp1;
+
+  // instantiations
+
+  assign gpio_i[31:8] = gpio_o[31:8];
+  assign gpio_i[63:35] = gpio_o[63:35];
+
+  assign adc_cnv = adc_cnv_w | (gpio_o[34] & ~gpio_t[34]);
+  assign gpio_i[34] = adc_cnv;
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iobuf_gp (
+    .dio_t(gpio_t[33:32]),
+    .dio_i(gpio_o[33:32]),
+    .dio_o(gpio_i[33:32]),
+    .dio_p({adc_gp1,    // device ready then ~data ready
+            adc_gp0})); // threshold event
+
+  ad_iobuf #(
+    .DATA_WIDTH(2)
+  ) i_iobuf_buttons (
+    .dio_t(gpio_t[1:0]),
+    .dio_i(gpio_o[1:0]),
+    .dio_o(gpio_i[1:0]),
+    .dio_p(btn));
+
+  ad_iobuf #(
+    .DATA_WIDTH(6)
+  ) i_iobuf_leds (
+    .dio_t(gpio_t[7:2]),
+    .dio_i(gpio_o[7:2]),
+    .dio_o(gpio_i[7:2]),
+    .dio_p(led));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (),
+    .spi0_csn_0_o (),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (1'b0),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o (),
+    .iic_ard_scl_io(iic_ard_scl),
+    .iic_ard_sda_io(iic_ard_sda),
+    .adc_spi_sclk(adc_spi_sclk),
+    .adc_spi_sdi(adc_spi_sdi),
+    .adc_spi_sdo(adc_spi_sdo),
+    .adc_spi_cs(adc_spi_cs),
+    .adc_spi_sdo_t(),
+    .adc_spi_three_wire(),
+    .adc_cnv(adc_cnv_w),
+    .adc_gp1_n(adc_gp1_n));
+
+endmodule