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dc2677a: add initial design
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Signed-off-by: Jem Geronimo <[email protected]>

dc2677a: c5soc: update Makefile

Signed-off-by: Jem Geronimo <[email protected]>

Readme.md: add build instructions

Signed-off-by: Jem Geronimo <[email protected]>

dc2677a_qsys.tcl: set CSn and PD low by default

Signed-off-by: Alexis Torreno <[email protected]>

fix spaces, indentations, and comments

Signed-off-by: Jem Geronimo <[email protected]>

dc2677a/Readme.md: add useful links, list of supported parts, and build instructions

Signed-off-by: Jem Geronimo <[email protected]>

edit copyright

Signed-off-by: Jem Geronimo <[email protected]>

add copyright and license header to all .tcl and .sdc files

Signed-off-by: Jem Geronimo <[email protected]>

dc2677a_qsys.tcl: remove empty line

Signed-off-by: Jem Geronimo <[email protected]>

dc2677a: Fix critical warnings

Fix critical warnings regarding unconnected pin by splitting the
system_top.v in system_top_cmos.v and system_top_lvds.v
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@jemfgeronimo
jemfgeronimo committed Sep 27, 2023
1 parent 5efade8 commit 78dcbb6
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Showing 15 changed files with 971 additions and 164 deletions.
10 changes: 5 additions & 5 deletions library/Makefile
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####################################################################################
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
################################################################################
################################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
####################################################################################
################################################################################
################################################################################

include ../quiet.mk

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6 changes: 3 additions & 3 deletions library/axi_ltc235x/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
###############################################################################

LIBRARY_NAME := axi_ltc235x

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8 changes: 4 additions & 4 deletions library/axi_ltc235x/axi_ltc235x.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -43,7 +43,7 @@ module axi_ltc235x #(
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter [0:0] LVDS_CMOS_N = 0,
parameter LVDS_CMOS_N = 0,
parameter LANE_0_ENABLE = 1,
parameter LANE_1_ENABLE = 1,
parameter LANE_2_ENABLE = 1,
Expand Down Expand Up @@ -146,8 +146,8 @@ module axi_ltc235x #(
LANE_2_ENABLE == 1 ? 1'b1 : 1'b0,
LANE_1_ENABLE == 1 ? 1'b1 : 1'b0,
LANE_0_ENABLE == 1 ? 1'b1 : 1'b0};
localparam [ 0:0] RD_RAW_DATA = 1'b1;
localparam [ 0:0] CMOS_OR_LVDS_N = ~LVDS_CMOS_N;
localparam RD_RAW_DATA = 1'b1;
localparam CMOS_OR_LVDS_N = ~LVDS_CMOS_N;
localparam [31:0] CONFIG = {RD_RAW_DATA, 5'b0, CMOS_OR_LVDS_N, 7'b0};

// internal registers
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157 changes: 76 additions & 81 deletions library/axi_ltc235x/axi_ltc235x_cmos.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -92,83 +92,83 @@ module axi_ltc235x_cmos #(

// internal registers

reg busy_m1;
reg busy_m2;
reg busy_m3;

reg [ 4:0] scki_counter = 5'h0;
reg [ 4:0] data_counter = 5'h0;

reg scki_i;
reg scki_d;

reg [BW:0] adc_lane_0;
reg [BW:0] adc_lane_1;
reg [BW:0] adc_lane_2;
reg [BW:0] adc_lane_3;
reg [BW:0] adc_lane_4;
reg [BW:0] adc_lane_5;
reg [BW:0] adc_lane_6;
reg [BW:0] adc_lane_7;

reg [BW:0] adc_data_init[7:0];
reg [BW:0] adc_data_store[7:0];

reg [ 2:0] lane_0_ch = 3'd0;
reg [ 2:0] lane_1_ch = 3'd0;
reg [ 2:0] lane_2_ch = 3'd0;
reg [ 2:0] lane_3_ch = 3'd0;
reg [ 2:0] lane_4_ch = 3'd0;
reg [ 2:0] lane_5_ch = 3'd0;
reg [ 2:0] lane_6_ch = 3'd0;
reg [ 2:0] lane_7_ch = 3'd0;

reg [ 3:0] adc_lane0_shift;
reg [ 3:0] adc_lane1_shift;
reg [ 3:0] adc_lane2_shift;
reg [ 3:0] adc_lane3_shift;
reg [ 3:0] adc_lane4_shift;
reg [ 3:0] adc_lane5_shift;
reg [ 3:0] adc_lane6_shift;
reg [ 3:0] adc_lane7_shift;

reg [ 3:0] adc_lane0_shift_d;
reg [ 3:0] adc_lane1_shift_d;
reg [ 3:0] adc_lane2_shift_d;
reg [ 3:0] adc_lane3_shift_d;
reg [ 3:0] adc_lane4_shift_d;
reg [ 3:0] adc_lane5_shift_d;
reg [ 3:0] adc_lane6_shift_d;
reg [ 3:0] adc_lane7_shift_d;

reg adc_valid_init;
reg adc_valid_init_d;

reg [ 7:0] ch_data_lock = 8'hff;
reg [ 7:0] ch_capture;
reg [ 7:0] ch_captured;

reg scko_d;
reg [7:0] sdo_d;

reg [ 4:0] sdi_index = 5'd23;

reg [23:0] softspan_next_int;
reg busy_m1;
reg busy_m2;
reg busy_m3;

reg [ 4:0] scki_counter = 5'h0;
reg [ 4:0] data_counter = 5'h0;

reg scki_i;
reg scki_d;

reg [BW:0] adc_lane_0;
reg [BW:0] adc_lane_1;
reg [BW:0] adc_lane_2;
reg [BW:0] adc_lane_3;
reg [BW:0] adc_lane_4;
reg [BW:0] adc_lane_5;
reg [BW:0] adc_lane_6;
reg [BW:0] adc_lane_7;

reg [BW:0] adc_data_init[7:0];
reg [BW:0] adc_data_store[7:0];

reg [ 2:0] lane_0_ch = 3'd0;
reg [ 2:0] lane_1_ch = 3'd0;
reg [ 2:0] lane_2_ch = 3'd0;
reg [ 2:0] lane_3_ch = 3'd0;
reg [ 2:0] lane_4_ch = 3'd0;
reg [ 2:0] lane_5_ch = 3'd0;
reg [ 2:0] lane_6_ch = 3'd0;
reg [ 2:0] lane_7_ch = 3'd0;

reg [ 3:0] adc_lane0_shift;
reg [ 3:0] adc_lane1_shift;
reg [ 3:0] adc_lane2_shift;
reg [ 3:0] adc_lane3_shift;
reg [ 3:0] adc_lane4_shift;
reg [ 3:0] adc_lane5_shift;
reg [ 3:0] adc_lane6_shift;
reg [ 3:0] adc_lane7_shift;

reg [ 3:0] adc_lane0_shift_d;
reg [ 3:0] adc_lane1_shift_d;
reg [ 3:0] adc_lane2_shift_d;
reg [ 3:0] adc_lane3_shift_d;
reg [ 3:0] adc_lane4_shift_d;
reg [ 3:0] adc_lane5_shift_d;
reg [ 3:0] adc_lane6_shift_d;
reg [ 3:0] adc_lane7_shift_d;

reg adc_valid_init;
reg adc_valid_init_d;

reg [ 7:0] ch_data_lock = 8'hff;
reg [ 7:0] ch_capture;
reg [ 7:0] ch_captured;

reg scko_d;
reg [ 7:0] sdo_d;

reg [ 4:0] sdi_index = 5'd23;

reg [23:0] softspan_next_int;

// internal wires

wire start_transfer_s;
wire start_transfer_s;

wire scki_cnt_rst;
wire scki_cnt_rst;

wire acquire_data;
wire acquire_data;

wire [17:0] adc_data_raw_s [7:0];
wire [31:0] adc_data_sign_s [7:0];
wire [31:0] adc_data_zero_s [7:0];
wire [31:0] adc_data_s [7:0];
wire [ 2:0] adc_ch_id_s [7:0];
wire [ 2:0] adc_softspan_s [7:0];
wire [17:0] adc_data_raw_s [7:0];
wire [31:0] adc_data_sign_s [7:0];
wire [31:0] adc_data_zero_s [7:0];
wire [31:0] adc_data_s [7:0];
wire [ 2:0] adc_ch_id_s [7:0];
wire [ 2:0] adc_softspan_s [7:0];

always @(posedge clk) begin
if (rst == 1'b1) begin
Expand All @@ -188,7 +188,7 @@ module axi_ltc235x_cmos #(
if (rst) begin
scki_counter <= 5'h0;
scki_i <= 1'b1;
scki_d <= 1'b0;
scki_d <= 1'b0;
end else begin
scki_d <= scki_i;
if (acquire_data == 1'b0) begin
Expand Down Expand Up @@ -287,14 +287,9 @@ module axi_ltc235x_cmos #(
end
end

/*
lane_X_ch - channel number that lane X has
e.g., lane_0_ch = 2, means lane 0 has channel 2
ch_data_lock[i] - locks channel i
e.g., ch_data_lock[7] = 1, means data from channel 7 has already been
sent to an active lane, channel 7 should now be locked.
Don't acquire data if all channels are all already locked.
*/
// lane_x_ch - channel corresponds to which lane, e.g. lane_0_ch stores the current channel lane 0 has
// ch_data_lock[i] - locks ch i, e.g. ch_data_lock[7] = 1 means data from channel 7 has already been sent to an active lane, channel 7 should now be locked
// dont acquire data if all channels are all already locked
always @(posedge clk) begin
if (start_transfer_s) begin
lane_0_ch <= 3'd0;
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4 changes: 4 additions & 0 deletions library/axi_ltc235x/axi_ltc235x_hw.tcl
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###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip

package require qsys 14.0
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