docs: i3c_controller regmap and docs

Update i3c_controller regmap. Include documentation pages for the i3c_controller library. Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Oct 2, 2023 · 66729e7 · 66729e7
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diff --git a/docs/index.rst b/docs/index.rst
@@ -13,8 +13,9 @@ HDL Reference Designs
    :caption: Libraries
    :hidden:
 
-   library/spi_engine/index
    library/axi_dmac/index
+   library/spi_engine/index
+   library/i3c_controller/index
 
 .. attention::
 

diff --git a/docs/library/i3c_controller/i3c_controller_core.rst b/docs/library/i3c_controller/i3c_controller_core.rst
@@ -0,0 +1,39 @@
+.. _i3c_controller core:
+
+I3C Controller Core
+================================================================================
+
+.. symbolator:: ../../../library/i3c_controller/i3c_controller_core/i3c_controller_core.v
+   :caption: i3c_controller_core
+
+The I3C Controller Core peripheral forms the heart of the I3C Controller.
+It is responsible for handling a I3C Controller commandsand translates it into low-level I3C bus transactions.
+
+Files
+-------------------------------------------------------------------------------
+
+.. list-table::
+   :widths: 25 75
+   :header-rows: 1
+
+   * - Name
+     - Description
+   * - :git-hdl:`master:library/i3c_controller/i3c_controller_core/i3c_controller_core.v`
+     - Verilog source for the peripheral.
+   * - :git-hdl:`master:library/i3c_controller/i3c_controller_core/i3c_controller_core.tcl`
+     - TCL script to generate the Vivado IP-integrator project for the peripheral.
+
+
+Configuration Parameters
+--------------------------------------------------------------------------------
+
+.. hdl-parameters::
+
+Signal and Interface Pins
+--------------------------------------------------------------------------------
+
+.. hdl-interfaces::
+
+Theory of Operation
+--------------------------------------------------------------------------------
+
diff --git a/docs/library/i3c_controller/i3c_controller_host_interface.rst b/docs/library/i3c_controller/i3c_controller_host_interface.rst
@@ -0,0 +1,67 @@
+.. _i3c_controller host_interface:
+
+I3C Controller Host Interface
+================================================================================
+
+.. symbolator:: ../../../library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v
+   :caption: i3c_controller_host_interface
+
+The I3C Controller Host Interface peripheral allows asynchronous interrupt-driven memory-mapped
+access to a I3C Controller Control Interface.
+This is typically used in combination with a software program to dynamically
+generate I3C transactions.
+
+The peripheral has also support for providing memory-mapped access to one or more
+:ref:`i3c_controller offload-control-interface` cores and change its content
+dynamically at runtime.
+
+Files
+--------------------------------------------------------------------------------
+
+.. list-table::
+   :widths: 25 75
+   :header-rows: 1
+
+   * - Name
+     - Description
+   * - :git-hdl:`master:library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v`
+     - Verilog source for the peripheral.
+   * - :git-hdl:`master:library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.tcl`
+     - TCL script to generate the Vivado IP-integrator project for the peripheral.
+
+Configuration Parameters
+--------------------------------------------------------------------------------
+
+.. hdl-parameters::
+
+Signal and Interface Pins
+--------------------------------------------------------------------------------
+
+.. hdl-interfaces::
+
+Register Map
+--------------------------------------------------------------------------------
+
+.. hdl-regmap::
+   :name: i3c_controller_host_interface
+
+Theory of Operation
+--------------------------------------------------------------------------------
+
+FIFOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+Synchronization Events
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+Interrupts
+--------------------------------------------------------------------------------
+
+
+FIFO Threshold Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+SYNC_EVENT Interrupt
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/library/i3c_controller/index.rst b/docs/library/i3c_controller/index.rst
@@ -0,0 +1,35 @@
+.. _i3c_controller:
+
+I3C Controller
+================================================================================
+
+.. toctree::
+   :hidden:
+
+   Host Interface<i3c_controller_host_interface>
+   Core Module<i3c_controller_core>
+   Interface<interface>
+
+I3C Controller is subset of the I3C specification to interface peripheral such
+as ADCs through I3C.
+
+Sub-modules
+--------------------------------------------------------------------------------
+
+* :ref:`i3c_controller host_interface`: Memory mapped software accessible
+  interface to a I3C Controller command stream and/or offload cores.
+* :ref:`i3c_controller core`: Main module which executes a I3C Controller command
+  stream and implements the I3C bus interface logic.
+
+Interfaces
+--------------------------------------------------------------------------------
+
+* :ref:`i3c_controller control-interface`: SPI Engine command stream.
+* :ref:`i3c_controller offload-control-interface`: Program the command stream
+  stored in a offload module.
+
+Software
+--------------------------------------------------------------------------------
+
+* :ref:`i3c_controller instruction-format`: Overview of the I3C Controller
+  instruction format.