cn0585: Remove/rename _fmcz folders

analogdevicesinc · Jul 23, 2024 · 74d3103 · 74d3103
1 parent 191b36e
commit 74d3103
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Showing 31 changed files with 60 additions and 42 deletions.
diff --git a/CI/scripts_hdl/matlab_processors.tcl b/CI/scripts_hdl/matlab_processors.tcl
@@ -3,13 +3,12 @@ proc preprocess_bd {project carrier rxtx} {
     puts "Preprocessing $project $carrier $rxtx"
 
     switch $project {
-        cn0585_fmcz {
+        cn0585 {
             # Disconnect the ADC PACK pins
-	    delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
-
+	          delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
 
             set sys_cstring "matlab $rxtx"
             sysid_gen_sys_init_file $sys_cstring
@@ -20,21 +19,21 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
 
            if {$rxtx == "rx"} {
-	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
+	           connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
              connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
              connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
              connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
            }
 
            if {$rxtx == "tx"} {
-	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
+	           connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
              connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
              connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
              connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
              connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
            }
 
-	   if {$rxtx == "tx" || $rxtx == "rxtx"} {
+	        if {$rxtx == "tx" || $rxtx == "rxtx"} {
 
             delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
             delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
@@ -45,14 +44,14 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
-	   }
-	    switch $carrier {
-              zed {
-                    set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
-                  }
-             }
+	    }
+	  switch $carrier {
+          zed {
+                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
+                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
+                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+              }
+          }
         }
     }
 }
diff --git a/.../+zed/hdlcoder_ref_design_customization.m → .../+zed/hdlcoder_ref_design_customization.m b/.../+zed/hdlcoder_ref_design_customization.m → .../+zed/hdlcoder_ref_design_customization.m
diff --git a/...gDevices/+cn0585_fmcz/+zed/plugin_board.m → ...AnalogDevices/+cn0585/+zed/plugin_board.m b/...gDevices/+cn0585_fmcz/+zed/plugin_board.m → ...AnalogDevices/+cn0585/+zed/plugin_board.m
diff --git a/...gDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m → ...AnalogDevices/+cn0585/+zed/plugin_rd_rx.m b/...gDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m → ...AnalogDevices/+cn0585/+zed/plugin_rd_rx.m
diff --git a/...evices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m → ...alogDevices/+cn0585/+zed/plugin_rd_rxtx.m b/...evices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m → ...alogDevices/+cn0585/+zed/plugin_rd_rxtx.m
diff --git a/...gDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m → ...AnalogDevices/+cn0585/+zed/plugin_rd_tx.m b/...gDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m → ...AnalogDevices/+cn0585/+zed/plugin_rd_tx.m
diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m
@@ -6,7 +6,7 @@
 pname = upper(project);
 ppath = project;
 if strcmpi(project, 'cn0585')
-    ppath = 'cn0585_fmcz';	
+    ppath = 'cn0585';	
 end
 
 % Construct reference design object

diff --git a/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl b/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl
@@ -5,11 +5,10 @@ proc preprocess_bd {project carrier rxtx} {
     switch $project {
         cn0585 {
             # Disconnect the ADC PACK pins
-	    delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
-	    delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
-
+	          delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
+	          delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
 
             set sys_cstring "matlab $rxtx"
             sysid_gen_sys_init_file $sys_cstring
@@ -20,21 +19,21 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
 
            if {$rxtx == "rx"} {
-	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
+	           connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
              connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
              connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
              connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
            }
 
            if {$rxtx == "tx"} {
-	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
+	           connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
              connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
              connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
              connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
              connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
            }
 
-	   if {$rxtx == "tx" || $rxtx == "rxtx"} {
+	        if {$rxtx == "tx" || $rxtx == "rxtx"} {
 
             delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
             delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
@@ -45,14 +44,14 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
             connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
-	   }
-	    switch $carrier {
-              zed {
-                    set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
-                  }
-             }
+	    }
+	  switch $carrier {
+          zed {
+                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
+                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
+                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+              }
+          }
         }
     }
 }
diff --git a/.../streaming/cn0585_fmcz/CN0585_streaming.m → ...mples/streaming/cn0585/CN0585_streaming.m b/.../streaming/cn0585_fmcz/CN0585_streaming.m → ...mples/streaming/cn0585/CN0585_streaming.m
diff --git a/...mo/CN0585_streaming_axi4lite_read_write.m → ...mo/CN0585_streaming_axi4lite_read_write.m b/...mo/CN0585_streaming_axi4lite_read_write.m → ...mo/CN0585_streaming_axi4lite_read_write.m
diff --git a/...585_host_axi4_lite_read_write_example.slx → ...585_host_axi4_lite_read_write_example.slx b/...585_host_axi4_lite_read_write_example.slx → ...585_host_axi4_lite_read_write_example.slx
diff --git a/...xi4_lite_demo/zynq-zed-adv7511-cn0585.dts → ...xi4_lite_demo/zynq-zed-adv7511-cn0585.dts b/...xi4_lite_demo/zynq-zed-adv7511-cn0585.dts → ...xi4_lite_demo/zynq-zed-adv7511-cn0585.dts
diff --git a/...led_sw_gpio_control_demo/+common/add_io.m → ...led_sw_gpio_control_demo/+common/add_io.m b/...led_sw_gpio_control_demo/+common/add_io.m → ...led_sw_gpio_control_demo/+common/add_io.m
diff --git a/...ommon/hdlcoder_ref_design_customization.m → ...ommon/hdlcoder_ref_design_customization.m b/...ommon/hdlcoder_ref_design_customization.m → ...ommon/hdlcoder_ref_design_customization.m
diff --git a/..._gpio_control_demo/+common/plugin_board.m → ..._gpio_control_demo/+common/plugin_board.m b/..._gpio_control_demo/+common/plugin_board.m → ..._gpio_control_demo/+common/plugin_board.m
diff --git a/..._sw_gpio_control_demo/+common/plugin_rd.m → ..._sw_gpio_control_demo/+common/plugin_rd.m b/..._sw_gpio_control_demo/+common/plugin_rd.m → ..._sw_gpio_control_demo/+common/plugin_rd.m
diff --git a/...sw_gpio_control_demo/+zed/+tx/add_tx_io.m → ...sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/...sw_gpio_control_demo/+zed/+tx/add_tx_io.m → ...sw_gpio_control_demo/+zed/+tx/add_tx_io.m
diff --git a/...d/+tx/hdlcoder_ref_design_customization.m → ...d/+tx/hdlcoder_ref_design_customization.m b/...d/+tx/hdlcoder_ref_design_customization.m → ...d/+tx/hdlcoder_ref_design_customization.m
diff --git a/...gpio_control_demo/+zed/+tx/plugin_board.m → ...gpio_control_demo/+zed/+tx/plugin_board.m b/...gpio_control_demo/+zed/+tx/plugin_board.m → ...gpio_control_demo/+zed/+tx/plugin_board.m
diff --git a/...sw_gpio_control_demo/+zed/+tx/plugin_rd.m → ...sw_gpio_control_demo/+zed/+tx/plugin_rd.m b/...sw_gpio_control_demo/+zed/+tx/plugin_rd.m → ...sw_gpio_control_demo/+zed/+tx/plugin_rd.m
diff --git a/...rol_demo/hdlworkflow_cn0585_gpio_zed_tx.m → ...rol_demo/hdlworkflow_cn0585_gpio_zed_tx.m b/...rol_demo/hdlworkflow_cn0585_gpio_zed_tx.m → ...rol_demo/hdlworkflow_cn0585_gpio_zed_tx.m
diff --git a/..._gpio_control_demo/testModel_Tx16and8.slx → ..._gpio_control_demo/testModel_Tx16and8.slx b/..._gpio_control_demo/testModel_Tx16and8.slx → ..._gpio_control_demo/testModel_Tx16and8.slx
diff --git a/...ting/cn0585_fmcz/cn0585_hdl/adi_build.tcl → ...targeting/cn0585/cn0585_hdl/adi_build.tcl b/...ting/cn0585_fmcz/cn0585_hdl/adi_build.tcl → ...targeting/cn0585/cn0585_hdl/adi_build.tcl
diff --git a/...eting/cn0585_fmcz/cn0585_hdl/build_bsp.sh → .../targeting/cn0585/cn0585_hdl/build_bsp.sh b/...eting/cn0585_fmcz/cn0585_hdl/build_bsp.sh → .../targeting/cn0585/cn0585_hdl/build_bsp.sh
@@ -2,7 +2,7 @@
 set -x
 cd "$(dirname "$0")"
 if [ -z "${HDLBRANCH}" ]; then
-HDLBRANCH='cn0585_pr'
+HDLBRANCH='main'
 fi
 
 # Script is designed to run from specific location

diff --git a/.../cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl → ...eting/cn0585/cn0585_hdl/fh_preprocess.tcl b/.../cn0585_fmcz/cn0585_hdl/fh_preprocess.tcl → ...eting/cn0585/cn0585_hdl/fh_preprocess.tcl
diff --git a/...585_fmcz/cn0585_hdl/matlab_processors.tcl → ...g/cn0585/cn0585_hdl/matlab_processors.tcl b/...585_fmcz/cn0585_hdl/matlab_processors.tcl → ...g/cn0585/cn0585_hdl/matlab_processors.tcl
diff --git a/...rgeting/cn0585_fmcz/cn0585_hdl/ports.json → ...es/targeting/cn0585/cn0585_hdl/ports.json b/...rgeting/cn0585_fmcz/cn0585_hdl/ports.json → ...es/targeting/cn0585/cn0585_hdl/ports.json
diff --git a/...5_fmcz/cn0585_hdl/system_project_rxtx.tcl → ...cn0585/cn0585_hdl/system_project_rxtx.tcl b/...5_fmcz/cn0585_hdl/system_project_rxtx.tcl → ...cn0585/cn0585_hdl/system_project_rxtx.tcl
diff --git a/..._gpio_control_demo/testModel_Tx16and8.slx → ..._gpio_control_demo/testModel_Tx16and8.slx b/..._gpio_control_demo/testModel_Tx16and8.slx → ..._gpio_control_demo/testModel_Tx16and8.slx
diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m
@@ -66,6 +66,11 @@ function CollectLogs(testCase,cfgb)
                 disp('Found workflow_task_CreateProject... copying');
                 movefile('workflow_task_CreateProject.log',[rdn,'_CreateProject_',cfgb.mode,'.log']);
             end
+            system(join(["find '",testCase.Folder,"' -name 'system_top_timing_summary_routed.rpt' | xargs -I '{}' cp {} ."],''));
+            if exist('system_top_timing_summary_routed.rpt','file')
+                disp('Found system_top_timing_summary_routed... copying');
+                movefile('system_top_timing_summary_routed.rpt',[rdn,'_timing_summary_',cfgb.mode,'.rpt']);
+            end
             system(join(["find '",testCase.Folder,"' -name 'workflow_task_BuildFPGABitstream.log' | xargs -I '{}' cp {} ."],''));
             if exist('workflow_task_BuildFPGABitstream.log','file')
                 disp('Found workflow_task_BuildFPGABitstream... copying');
@@ -109,6 +114,15 @@ function CollectLogs(testCase,cfgb)
                     'vivado_version',vivado_version,'mode',mode);
                 cfg = [cfg(:)',{cfg1},{cfg2},{cfg3}];
 
+		mode = 'tx_rx';
+                h2 = str2func([s,'.',variants{k},'.plugin_rd_txrx']);h2 = h2();
+                ReferenceDesignName = h2.ReferenceDesignName;
+                vivado_version = h2.SupportedToolVersion{:};
+                cfg4 = struct('Board',h1,...
+                    'ReferenceDesignName',ReferenceDesignName,...
+                    'vivado_version',vivado_version,'mode',mode);
+                cfg = [cfg(:)',{cfg1},{cfg2},{cfg4}];
+
             end
 
         end
@@ -124,7 +138,7 @@ function CollectLogs(testCase,cfgb)
                 assert(0);
             elseif strcmp(s{2},'adrv9361z7035') || ...
                     strcmp(s{2},'adrv9364z7020')
-                h = str2func([strjoin(s(1:2),'.'),'.common.plugin_board']);
+                h = str2func([strjoin(s(1:2),'.'),'.plugin_board']);
             else
                 h = str2func([strjoin(s(1:end-1),'.'),'.plugin_board']);
             end
@@ -138,10 +152,16 @@ function CollectLogs(testCase,cfgb)
         end
 
         function setVivadoPath(~,vivado)
-            if ispc
-                pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat'];
-            elseif isunix
-                pathname = ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
+            CUSTOM_VIVADO_PATH = getenv('CUSTOM_VIVADO_PATH');
+            if ~isempty(CUSTOM_VIVADO_PATH)
+                pathname = CUSTOM_VIVADO_PATH;
+                fprintf('Using custom Vivado path: %s\n',pathname);
+            else
+                if ispc
+                    pathname = ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat'];
+                elseif isunix
+                    pathname = ['/emea/mediadata/opt/Xilinx/Vivado/',vivado,'/bin/vivado'];
+                end
             end
             assert(exist(pathname,'file')>0,'Correct version of Vivado is unavailable or in a non-standard location');
             hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ...
@@ -183,4 +203,4 @@ function testMain(testCase, configs, SynthesizeDesign)
             end
         end
     end
-end
+end
diff --git a/test/build_design.m b/test/build_design.m
@@ -29,7 +29,7 @@
 
 % Specify the top level project directory
 hWC.ProjectFolder = folder;
-hWC.ReferenceDesignToolVersion = vivado_version;
+hWC.ReferenceDesignToolVersion = '2023.2';
 hWC.IgnoreToolVersionMismatch = true;
 hWC.AllowUnsupportedToolVersion = true;