Merge pull request #84 from analogdevicesinc/md_update

Deleted copies of .md files in CI/gen_doc/docs
analogdevicesinc · Aug 16, 2022 · d59c430 · d59c430
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diff --git a/CI/gen_doc/docs/_pages/install.md b/CI/gen_doc/docs/_pages/install.md
@@ -56,7 +56,7 @@ The Transceiver Toolbox itself can be installed either from:
 
 To install the toolbox from within MATLAB using the Add-On Explorer, first launch the Explorer from MATLAB's Home tab:
 
-<img class="screenshot" src="/assets/add_ex.png">
+<img class="screenshot" src="../assets/add_ex.png">
 
 Search for the toolbox:
 

diff --git a/CI/gen_doc/docs/_pages/targeting.md b/CI/gen_doc/docs/_pages/targeting.md
@@ -1,7 +1,7 @@
-{% include 'header.tmpl' %}
+
 # HDL Targeting with HDL-Coder
 
-Transceiver Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and transceiver based reference designs. This support is based on the Zynq HDL-Coder and support
+High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and high-speed based reference designs. This support is based on the Zynq HDL-Coder and support
 
 <img src="../assets/MATLAB_HDL_Ref_Design.png">
 
@@ -11,3 +11,47 @@ Transceiver Toolbox supports the IP Core generation flow from MathWorks which al
 
 ## Getting Started
 
+To perform targeting will require FPGA vendor tools for the FPGA system. For Xilinx this will be Vivado and the toolbox will require specific versions for each release. For the current release this is Vivado 2019.1. Using other versions are not supported. To build the necessary BOOT.BIN files will require the Xilinx SDK as well.
+
+Once you have the installed the necessary 3rd party tools MATLAB needs to be told where they are installed by use of the [hdlsetuptoolpath](https://www.mathworks.com/help/hdlcoder/ref/hdlsetuptoolpath.html) command. For Windows the following MATLAB command can be used:
+
+```matlab
+hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.1\bin\vivado.bat');
+```
+
+or Linux:
+
+```matlab
+hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', '/opt/Xilinx/Vivado/2019.1/bin/vivado');
+```
+
+Please change the tool path if it is different on your system.
+
+### Checking For Supported Designs
+
+To verify that the ADI reference designs are available to [HDL Workflow Advisor](https://www.mathworks.com/help/hdlcoder/ug/overview-of-workflows-in-hdl-workflow-advisor.html) a Simulink model needs to be opened. To do so launch Simulink with the following command:
+
+```matlab
+simulink
+```
+
+After it launches open a "Blank DUT" model from the "HDL Coder" dropdown of the Simulink Start Page.
+
+<img src="../assets/simulink_blank_dut.png">
+<!-- <img src="/tmp/HighSpeedConverterToolbox/doc/assets/simulink_blank_dut.png"> -->
+
+After the model opens, click on the green subsystem to select it. Then open the "Apps" tap, open the apps menu and
+scroll down to HDL-Coder.
+
+<img src="../assets/simulink_hdl_coder.png">
+<!-- <img src="/tmp/HighSpeedConverterToolbox/doc/assets/simulink_hdl_coder.png"> -->
+
+This will open the HDL-Coder menu, from here the Workflow Advisor is selectable. Click on it to launch the advisor.
+
+<img src="../assets/simulink_wa.png">
+<!-- <img src="/tmp/HighSpeedConverterToolbox/doc/assets/simulink_wa.png"> -->
+
+Once launch go to Step 1.1 on the left side column. Then on the right side of the window select "IP Core Generation" for "Target workflow". Then the ADI reference designs should be available in the "Target platform" menu as so:
+
+<img src="../assets/hwa_11_crop.png">
+<!-- <img src="/tmp/HighSpeedConverterToolbox/doc/assets/hwa_11_crop.png"> -->
diff --git a/CI/gen_doc/docs/examples.md b/CI/gen_doc/docs/examples.md
diff --git a/CI/gen_doc/docs/index.md b/CI/gen_doc/docs/index.md
diff --git a/CI/gen_doc/docs/install.md b/CI/gen_doc/docs/install.md
diff --git a/CI/gen_doc/docs/models.md b/CI/gen_doc/docs/models.md
diff --git a/CI/gen_doc/docs/streaming.md b/CI/gen_doc/docs/streaming.md
diff --git a/CI/gen_doc/docs/support.md b/CI/gen_doc/docs/support.md