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alaindargelas committed Jan 9, 2024
1 parent f4ef909 commit 0d00a6a
Showing 1 changed file with 4 additions and 3 deletions.
7 changes: 4 additions & 3 deletions frontends/systemverilog/uhdm_ast.cc
Original file line number Diff line number Diff line change
Expand Up @@ -745,9 +745,8 @@ static void convert_packed_unpacked_range(AST::AstNode *wire_node)
return true;
if (unpacked_ranges.size() > 1)
return true;
if (wire_node->attributes.count(ID::wiretype)) {
if (wire_node->attributes.count(ID::wiretype))
return true;
}
if (wire_node->type == AST::AST_PARAMETER)
return true;
if (wire_node->type == AST::AST_LOCALPARAM)
Expand Down Expand Up @@ -2974,9 +2973,11 @@ void UhdmAst::process_array_var()
// current_node->children = std::move(node->children);
copy_packed_unpacked_attribute(node, current_node);
} else {

auto wiretype_node = new AST::AstNode(AST::AST_WIRETYPE);
wiretype_node->str = node->str;
// wiretype needs to be 1st node
// current_node->children.push_back(wiretype_node);
// wiretype needs to be 1st node
current_node->children.insert(current_node->children.begin(), wiretype_node);
current_node->is_custom_type = true;
}
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