Ring3: Some drafts.

acidanthera · Dec 25, 2023 · 2b27afe · 2b27afe
1 parent b83765b
commit 2b27afe
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diff --git a/UefiCpuPkg/Library/CpuArchLib/CpuGdt.c b/UefiCpuPkg/Library/CpuArchLib/CpuGdt.c
@@ -183,6 +183,60 @@ STATIC GDT_ENTRIES  mGdtTemplate = {
     .G                  = 0,
     .BaseAddress_31_24  = 0x0,
   },
+  .Ring3Data64 = {
+    .SegmentLimit_15_0        = 0xFFFF,
+    .BaseAddress_15_0         = 0x0,
+    .BaseAddress_23_16        = 0x0,
+
+    .Accessed                 = 0,
+    .Writable                 = 1,
+    .ExpansionDirection       = 0,
+    .IsCode                   = 0,
+    .IsNotSystemSegment       = 1,
+    .DescriptorPrivilegeLevel = 3,
+    .SegmentPresent           = 1,
+
+    .SegmentLimit_19_16       = 0xF,
+    .Available                = 0,
+    .Reserved                 = 0,
+    .UpperBound               = 1,
+    .Granularity              = 1,
+    .BaseAddress_31_24        = 0x0
+  },
+  .Ring3Code64 = { // SetCodeSelector () | 5.8.6 Returning from a Called Procedure
+    .Reserved1                = 0x0,
+    .Reserved2                = 0x0,
+
+    .Accessed                 = 0,
+    .Readable                 = 1,
+    .Conforming               = 0,
+    .IsCode                   = 1,
+    .IsNotSystemSegment       = 1,
+    .DescriptorPrivilegeLevel = 3,
+    .SegmentPresent           = 1,
+
+    .Reserved3                = 0x0,
+    .Available                = 0,
+    .LongMode                 = 1,
+    .Is32Bit                  = 0,
+    .Granularity              = 1,
+    .Reserved4                = 0x0
+  },
+  // .FromRing3ToRing0 = {
+  //   .Common.OffsetInSegment_15_0     = 0x?,
+  //   .Common.SegmentSelector          = (UINT16)LINEAR_CODE64_SEL,
+  //
+  //   .Common.ParameterCount           = 0,
+  //   .Common.Reserved                 = 0,
+  //
+  //   .Common.Type                     = 0xC,
+  //   .Common.IsNotSystemSegment       = 0,
+  //   .Common.DescriptorPrivilegeLevel = 3,
+  //   .Common.SegmentPresent           = 1,
+  //   .Common.OffsetInSegment_31_16    = 0x?,
+  //   .OffsetInSegment_63_31           = 0x?,
+  //   .Reserved                        = 0x0
+  // },
 };
 
 /**

diff --git a/UefiCpuPkg/Library/CpuArchLib/CpuGdt.h b/UefiCpuPkg/Library/CpuArchLib/CpuGdt.h
@@ -159,6 +159,9 @@ typedef struct {
   DATA_SEGMENT_32    LinearData64;
   CODE_SEGMENT_64    LinearCode64;
   SEGMENT_DESCRIPTOR Spare5;
+  DATA_SEGMENT_32    Ring3Data64;
+  CODE_SEGMENT_64    Ring3Code64;
+  // CALL_GATE_64       FromRing3ToRing0;
 } GDT_ENTRIES;
 
 #pragma pack ()
@@ -172,6 +175,8 @@ typedef struct {
 #define LINEAR_DATA64_SEL  OFFSET_OF (GDT_ENTRIES, LinearData64)
 #define LINEAR_CODE64_SEL  OFFSET_OF (GDT_ENTRIES, LinearCode64)
 #define SPARE5_SEL         OFFSET_OF (GDT_ENTRIES, Spare5)
+#define RING3_DATA64_SEL   OFFSET_OF (GDT_ENTRIES, Ring3Data64)
+#define RING3_CODE64_SEL   OFFSET_OF (GDT_ENTRIES, Ring3Code64)
 
 #if defined (MDE_CPU_IA32)
 #define CPU_CODE_SEL  LINEAR_CODE_SEL

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -249,6 +249,8 @@ ArchSetupExceptionStack (
     IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
   }
 
+  // Tss->RSP0 = %rsp
+
   //
   // Publish GDT
   //
-Original file line number
+Diff line change
@@ Expand Up / @@ -249,6 +249,8 @@ ArchSetupExceptionStack ( @@
         IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
       }
+      // Tss->RSP0 = %rsp
       //
       // Publish GDT
       //
@@ Expand Down @@