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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999677653 ""} | ||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999677654 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:54:37 2017 " "Processing started: Wed Nov 29 18:54:37 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999677654 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1511999677654 ""} | ||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1511999677654 ""} | ||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1511999679168 ""} | ||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1511999679235 ""} | ||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "499 " "Peak virtual memory: 499 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:54:40 2017 " "Processing ended: Wed Nov 29 18:54:40 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1511999680029 ""} |
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<?xml version="1.0" ?> | ||
<LOG_ROOT> | ||
<PROJECT NAME="gA6_lab5"> | ||
</PROJECT> | ||
</LOG_ROOT> |
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v1 |
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Quartus_Version = Version 13.0.0 Build 156 04/24/2013 SJ Web Edition | ||
Version_Index = 302029824 | ||
Creation_Time = Thu Nov 30 11:17:41 2017 |
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999705103 ""} | ||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:55:04 2017 " "Processing started: Wed Nov 29 18:55:04 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} | ||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5 " "Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} | ||
{ "Info" "IWSC_DONE_HDL_GENERATION" "gA6_lab5.vo C:/home/abbas/dsd_A6/lab5/simulation/modelsim/ simulation " "Generated file gA6_lab5.vo in folder \"C:/home/abbas/dsd_A6/lab5/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1511999705741 ""} | ||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "459 " "Peak virtual memory: 459 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:55:05 2017 " "Processing ended: Wed Nov 29 18:55:05 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} |
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|gA6_lab5 | ||
hit <= gA6_computer:inst.hit | ||
clk => gA6_computer:inst.clk | ||
clk => gA6_winner:inst1.clk | ||
rst => gA6_computer:inst.rst | ||
turn => gA6_computer:inst.turn | ||
sum[0] => gA6_computer:inst.sum[0] | ||
sum[1] => gA6_computer:inst.sum[1] | ||
sum[2] => gA6_computer:inst.sum[2] | ||
sum[3] => gA6_computer:inst.sum[3] | ||
sum[4] => gA6_computer:inst.sum[4] | ||
sum[5] => gA6_computer:inst.sum[5] | ||
done <= gA6_computer:inst.done | ||
player_wins <= gA6_winner:inst1.player_wins | ||
player_sum[0] => gA6_winner:inst1.player_sum[0] | ||
player_sum[1] => gA6_winner:inst1.player_sum[1] | ||
player_sum[2] => gA6_winner:inst1.player_sum[2] | ||
player_sum[3] => gA6_winner:inst1.player_sum[3] | ||
player_sum[4] => gA6_winner:inst1.player_sum[4] | ||
player_sum[5] => gA6_winner:inst1.player_sum[5] | ||
dealer_wins <= gA6_winner:inst1.dealer_wins | ||
led_display1[0] <= gA6_winner:inst1.led_display1[0] | ||
led_display1[1] <= gA6_winner:inst1.led_display1[1] | ||
led_display1[2] <= gA6_winner:inst1.led_display1[2] | ||
led_display1[3] <= gA6_winner:inst1.led_display1[3] | ||
led_display1[4] <= gA6_winner:inst1.led_display1[4] | ||
led_display1[5] <= gA6_winner:inst1.led_display1[5] | ||
led_display1[6] <= gA6_winner:inst1.led_display1[6] | ||
led_display2[0] <= gA6_winner:inst1.led_display2[0] | ||
led_display2[1] <= gA6_winner:inst1.led_display2[1] | ||
led_display2[2] <= gA6_winner:inst1.led_display2[2] | ||
led_display2[3] <= gA6_winner:inst1.led_display2[3] | ||
led_display2[4] <= gA6_winner:inst1.led_display2[4] | ||
led_display2[5] <= gA6_winner:inst1.led_display2[5] | ||
led_display2[6] <= gA6_winner:inst1.led_display2[6] | ||
led_display3[0] <= gA6_winner:inst1.led_display3[0] | ||
led_display3[1] <= gA6_winner:inst1.led_display3[1] | ||
led_display3[2] <= gA6_winner:inst1.led_display3[2] | ||
led_display3[3] <= gA6_winner:inst1.led_display3[3] | ||
led_display3[4] <= gA6_winner:inst1.led_display3[4] | ||
led_display3[5] <= gA6_winner:inst1.led_display3[5] | ||
led_display3[6] <= gA6_winner:inst1.led_display3[6] | ||
led_display4[0] <= gA6_winner:inst1.led_display4[0] | ||
led_display4[1] <= gA6_winner:inst1.led_display4[1] | ||
led_display4[2] <= gA6_winner:inst1.led_display4[2] | ||
led_display4[3] <= gA6_winner:inst1.led_display4[3] | ||
led_display4[4] <= gA6_winner:inst1.led_display4[4] | ||
led_display4[5] <= gA6_winner:inst1.led_display4[5] | ||
led_display4[6] <= gA6_winner:inst1.led_display4[6] | ||
state_out[0] <= gA6_computer:inst.state_out[0] | ||
state_out[1] <= gA6_computer:inst.state_out[1] | ||
sum_out[0] <= gA6_computer:inst.sum_out[0] | ||
sum_out[1] <= gA6_computer:inst.sum_out[1] | ||
sum_out[2] <= gA6_computer:inst.sum_out[2] | ||
sum_out[3] <= gA6_computer:inst.sum_out[3] | ||
sum_out[4] <= gA6_computer:inst.sum_out[4] | ||
sum_out[5] <= gA6_computer:inst.sum_out[5] | ||
|
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|gA6_lab5|gA6_computer:inst | ||
clk => sum_out[0]~reg0.CLK | ||
clk => sum_out[1]~reg0.CLK | ||
clk => sum_out[2]~reg0.CLK | ||
clk => sum_out[3]~reg0.CLK | ||
clk => sum_out[4]~reg0.CLK | ||
clk => sum_out[5]~reg0.CLK | ||
clk => done~reg0.CLK | ||
clk => hit~reg0.CLK | ||
clk => \computer:state[0].CLK | ||
clk => \computer:state[1].CLK | ||
rst => sum_out[0]~reg0.ACLR | ||
rst => sum_out[1]~reg0.ACLR | ||
rst => sum_out[2]~reg0.ACLR | ||
rst => sum_out[3]~reg0.ACLR | ||
rst => sum_out[4]~reg0.ACLR | ||
rst => sum_out[5]~reg0.ACLR | ||
rst => done~reg0.ACLR | ||
rst => hit~reg0.ACLR | ||
rst => \computer:state[0].ACLR | ||
rst => \computer:state[1].ACLR | ||
turn => state.OUTPUTSELECT | ||
turn => state.OUTPUTSELECT | ||
sum[0] => LessThan0.IN12 | ||
sum[0] => sum_out[0]~reg0.DATAIN | ||
sum[1] => LessThan0.IN11 | ||
sum[1] => sum_out[1]~reg0.DATAIN | ||
sum[2] => LessThan0.IN10 | ||
sum[2] => sum_out[2]~reg0.DATAIN | ||
sum[3] => LessThan0.IN9 | ||
sum[3] => sum_out[3]~reg0.DATAIN | ||
sum[4] => LessThan0.IN8 | ||
sum[4] => sum_out[4]~reg0.DATAIN | ||
sum[5] => LessThan0.IN7 | ||
sum[5] => sum_out[5]~reg0.DATAIN | ||
hit <= hit~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[0] <= sum_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[1] <= sum_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[2] <= sum_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[3] <= sum_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[4] <= sum_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
sum_out[5] <= sum_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
state_out[0] <= \computer:state[0].DB_MAX_OUTPUT_PORT_TYPE | ||
state_out[1] <= \computer:state[1].DB_MAX_OUTPUT_PORT_TYPE | ||
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|gA6_lab5|gA6_winner:inst1 | ||
clk => led_display4[0]~reg0.CLK | ||
clk => led_display4[1]~reg0.CLK | ||
clk => led_display4[2]~reg0.CLK | ||
clk => led_display4[3]~reg0.CLK | ||
clk => led_display4[4]~reg0.CLK | ||
clk => led_display4[5]~reg0.CLK | ||
clk => led_display4[6]~reg0.CLK | ||
clk => led_display3[0]~reg0.CLK | ||
clk => led_display3[1]~reg0.CLK | ||
clk => led_display3[2]~reg0.CLK | ||
clk => led_display3[3]~reg0.CLK | ||
clk => led_display3[4]~reg0.CLK | ||
clk => led_display3[5]~reg0.CLK | ||
clk => led_display3[6]~reg0.CLK | ||
clk => led_display2[0]~reg0.CLK | ||
clk => led_display2[1]~reg0.CLK | ||
clk => led_display2[2]~reg0.CLK | ||
clk => led_display2[3]~reg0.CLK | ||
clk => led_display2[4]~reg0.CLK | ||
clk => led_display2[5]~reg0.CLK | ||
clk => led_display2[6]~reg0.CLK | ||
clk => led_display1[0]~reg0.CLK | ||
clk => led_display1[1]~reg0.CLK | ||
clk => led_display1[2]~reg0.CLK | ||
clk => led_display1[3]~reg0.CLK | ||
clk => led_display1[4]~reg0.CLK | ||
clk => led_display1[5]~reg0.CLK | ||
clk => led_display1[6]~reg0.CLK | ||
clk => dealer_wins~reg0.CLK | ||
clk => player_wins~reg0.CLK | ||
clk => \dealer:d_win.CLK | ||
clk => \dealer:p_win.CLK | ||
player_sum[0] => LessThan0.IN12 | ||
player_sum[0] => LessThan2.IN6 | ||
player_sum[0] => LessThan3.IN6 | ||
player_sum[0] => Equal0.IN5 | ||
player_sum[1] => LessThan0.IN11 | ||
player_sum[1] => LessThan2.IN5 | ||
player_sum[1] => LessThan3.IN5 | ||
player_sum[1] => Equal0.IN4 | ||
player_sum[2] => LessThan0.IN10 | ||
player_sum[2] => LessThan2.IN4 | ||
player_sum[2] => LessThan3.IN4 | ||
player_sum[2] => Equal0.IN3 | ||
player_sum[3] => LessThan0.IN9 | ||
player_sum[3] => LessThan2.IN3 | ||
player_sum[3] => LessThan3.IN3 | ||
player_sum[3] => Equal0.IN2 | ||
player_sum[4] => LessThan0.IN8 | ||
player_sum[4] => LessThan2.IN2 | ||
player_sum[4] => LessThan3.IN2 | ||
player_sum[4] => Equal0.IN1 | ||
player_sum[5] => LessThan0.IN7 | ||
player_sum[5] => LessThan2.IN1 | ||
player_sum[5] => LessThan3.IN1 | ||
player_sum[5] => Equal0.IN0 | ||
dealer_sum[0] => LessThan1.IN12 | ||
dealer_sum[0] => LessThan2.IN12 | ||
dealer_sum[0] => LessThan3.IN12 | ||
dealer_sum[0] => Equal0.IN11 | ||
dealer_sum[1] => LessThan1.IN11 | ||
dealer_sum[1] => LessThan2.IN11 | ||
dealer_sum[1] => LessThan3.IN11 | ||
dealer_sum[1] => Equal0.IN10 | ||
dealer_sum[2] => LessThan1.IN10 | ||
dealer_sum[2] => LessThan2.IN10 | ||
dealer_sum[2] => LessThan3.IN10 | ||
dealer_sum[2] => Equal0.IN9 | ||
dealer_sum[3] => LessThan1.IN9 | ||
dealer_sum[3] => LessThan2.IN9 | ||
dealer_sum[3] => LessThan3.IN9 | ||
dealer_sum[3] => Equal0.IN8 | ||
dealer_sum[4] => LessThan1.IN8 | ||
dealer_sum[4] => LessThan2.IN8 | ||
dealer_sum[4] => LessThan3.IN8 | ||
dealer_sum[4] => Equal0.IN7 | ||
dealer_sum[5] => LessThan1.IN7 | ||
dealer_sum[5] => LessThan2.IN7 | ||
dealer_sum[5] => LessThan3.IN7 | ||
dealer_sum[5] => Equal0.IN6 | ||
player_wins <= player_wins~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
dealer_wins <= dealer_wins~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[0] <= led_display1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[1] <= led_display1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[2] <= led_display1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[3] <= led_display1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[4] <= led_display1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[5] <= led_display1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display1[6] <= led_display1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[0] <= led_display2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[1] <= led_display2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[2] <= led_display2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[3] <= led_display2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[4] <= led_display2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[5] <= led_display2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display2[6] <= led_display2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[0] <= led_display3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[1] <= led_display3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[2] <= led_display3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[3] <= led_display3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[4] <= led_display3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[5] <= led_display3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display3[6] <= led_display3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[0] <= led_display4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[1] <= led_display4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[2] <= led_display4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[3] <= led_display4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[4] <= led_display4[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[5] <= led_display4[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
led_display4[6] <= led_display4[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE | ||
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<TABLE> | ||
<TR bgcolor="#C0C0C0"> | ||
<TH>Hierarchy</TH> | ||
<TH>Input</TH> | ||
<TH>Constant Input</TH> | ||
<TH>Unused Input</TH> | ||
<TH>Floating Input</TH> | ||
<TH>Output</TH> | ||
<TH>Constant Output</TH> | ||
<TH>Unused Output</TH> | ||
<TH>Floating Output</TH> | ||
<TH>Bidir</TH> | ||
<TH>Constant Bidir</TH> | ||
<TH>Unused Bidir</TH> | ||
<TH>Input only Bidir</TH> | ||
<TH>Output only Bidir</TH> | ||
</TR> | ||
<TR > | ||
<TD >inst1</TD> | ||
<TD >13</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >30</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
</TR> | ||
<TR > | ||
<TD >inst</TD> | ||
<TD >9</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >10</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
<TD >0</TD> | ||
</TR> | ||
</TABLE> |
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; Legal Partition Candidates ; | ||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ | ||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; | ||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ | ||
; inst1 ; 13 ; 0 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; | ||
; inst ; 9 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; | ||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
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v1 |
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