Pre-commit fixes

Xilinx · Aug 3, 2023 · 7d5a8b6 · 7d5a8b6
1 parent 4dc1694
commit 7d5a8b6
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py
@@ -294,9 +294,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType,
             # bit width minimization logic in the MVAU and VVAU is exact and should be
             # less than or equal to this calculation
             exp_adt = calculate_accumulator_bit_width(inst, model)
-            assert (
-                cur_adt.bitwidth() <= exp_adt.bitwidth()
-            ), "Mismatched accumulation data types"
+            assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types"
 
             # if there is no activation, outputDataType = accDataType
             if inst.get_nodeattr("noActivation"):